公开(公告)号：US20230070995A1

公开(公告)日：2023-03-09

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20240012769A1

公开(公告)日：2024-01-11

申请号：US18370621

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Manish DAVE ,  Vered BAR BRACHA ,  Bradley A. BURRES ,  Uzair QURESHI ,  Joseph GRECCO ,  Paul KAPPLER ,  Dirk F. BLEVINS ,  Mukesh Gangadhar BHAVANI VENKATESAN ,  Hariharan M ,  Marek PIOTROWSKI ,  Dhanya PILLAI ,  John MANGAN ,  Mandar CHINCHOLKAR ,  Eoin WALSH ,  Sumit MOHAN ,  Ned SMITH ,  Tushar Sudhakar GOHAD

IPC: G06F13/16 ,  G06F11/20

CPC classification number: G06F13/1668 ,  G06F11/2017 ,  G06F2201/80

Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a network interface, a direct memory access (DMA) circuitry, a host interface, memory, one or more processors, and circuitry to: based on a configuration of operation specifying a standalone operation, cause the network interface device to operate in standalone to execute one or more applications and based on a configuration of operation specifying a companion operation, cause the network interface device to operate in companion to provide at least one host system with access to one or more hardware resources accessible by the network interface device.

公开(公告)号：US20210073047A1

公开(公告)日：2021-03-11

申请号：US16642563

申请日：2017-09-30

Applicant: INTEL CORPORATION

Inventor： Malini K. BHANDARU ,  Sundar NADATHUR ,  Joseph GRECCO ,  Roman DOBOSZ ,  Yongfeng DU

IPC: G06F9/50 ,  H04L12/24

Abstract: Technologies for managing accelerator resources include a cloud resource manager (102) to receive accelerator usage information from each of a plurality of node compute devices (104) and task parameters of a task to be performed. The cloud resource manager (102) accesses a task distribution policy, determines a destination node compute device (104) of the plurality of node compute devices (104) based on the task parameters and the task distribution policy, and assigns the task to the destination node compute device (104).

公开(公告)号：US20230121778A1

公开(公告)日：2023-04-20

申请号：US18067050

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Joseph GRECCO ,  Mukesh Gangadhar BHAVANI VENKATESAN ,  Hariharan M

IPC: G06F21/62

Abstract: Various examples relate to apparatuses, devices, methods, computer systems and computer programs for handling remote procedure calls. A non-transitory, computer-readable medium comprises machine-readable instructions that, when the program code is executed on a processor of a requesting host, causes the processor to provide an interface for locally receiving remote procedure calls from a plurality of threads of a computer program, and forward, upon receiving a remote procedure call from one of the threads of the computer program, the remote procedure call to a providing host that provides the functionality associated with the remote procedure call, wherein the remote procedure call is forwarded together with information on the thread having issued the remote procedure call.

公开(公告)号：US20210073161A1

公开(公告)日：2021-03-11

申请号：US17088513

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Susanne M. BALLE ,  Evan CUSTODIO ,  Francesc GUIM BERNAT ,  Sujoy SEN ,  Slawomir PUTYRSKI ,  Paul DORMITZER ,  Joseph GRECCO

IPC: G06F13/40 ,  G06F13/36

Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

公开(公告)号：US20200174841A1

公开(公告)日：2020-06-04

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.