公开(公告)号：US20240314072A1

公开(公告)日：2024-09-19

申请号：US18417570

申请日：2024-01-19

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L45/74 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/90

CPC classification number: H04L45/742 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/9068

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20210112003A1

公开(公告)日：2021-04-15

申请号：US17129756

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/861 ,  G06F12/1081 ,  H04L12/773

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US20200174841A1

公开(公告)日：2020-06-04

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20230070995A1

公开(公告)日：2023-03-09

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20190297015A1

公开(公告)日：2019-09-26

申请号：US16435328

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Rajesh M. SANKARAN ,  Ashok RAJ ,  Nrupal JANI ,  Parthasarathy SARANGAM ,  Robert O. SHARP

IPC: H04L12/747 ,  G06F13/28 ,  H04L12/773 ,  G06F12/1081 ,  H04L12/861

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.