公开(公告)号：US20230070995A1

公开(公告)日：2023-03-09

申请号：US17884244

申请日：2022-08-09

Applicant: Intel Corporation

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.

公开(公告)号：US20200174841A1

公开(公告)日：2020-06-04

申请号：US16619442

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Pratik M. MAROLIA ,  Aaron J. GRIER ,  Henry M. MITCHEL ,  Joseph GRECCO ,  Michael C. ADLER ,  Utkarsh Y. KAKAIYA ,  Joshua D. FENDER ,  Sundar NADATHUR ,  Nagabhushan CHITLUR

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/48

Abstract: A system comprising an accelerator circuit comprising an accelerator function unit to implement a first function, and one or more device feature header (DFH) circuits to provide attributes associated with the accelerator function unit, and a processor to retrieve the attributes of the accelerator function unit by traversing a device feature list (DFL) referencing the one or more DFH circuits, execute, based on the attributes, an application encoding the first function to cause the accelerator function unit to perform the first function.