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    PACKET BASED IN-LINE PROCESSING FOR DATA CENTER ENVIRONMENTS
    1.
    发明公开
    PACKET BASED IN-LINE PROCESSING FOR DATA CENTER ENVIRONMENTS 审中-公开

    公开(公告)号：US20230344894A1

    公开(公告)日：2023-10-26

    申请号：US18216524

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Susanne M. BALLE ,  Shihwei CHIEN ,  Andrzej KURIATA ,  Nagabhushan CHITLUR

    IPC: H04L67/025

    CPC classification number: H04L67/025

    Abstract: An apparatus is described. The apparatus includes a host side interface to couple to one or more central processing units (CPUs) that support multiple microservice endpoints. The apparatus includes a network interface to receive from a network a packet having multiple frames that belong to different streams, the multiple frames formatted according to a text transfer protocol. The apparatus includes circuitry to: process the frames according to the text transfer protocol and build content of a microservice functional call embedded within a message that one of the frames transports; and, execute the microservice function call.

    REMOTE STORAGE FOR HARDWARE MICROSERVICES HOSTED ON XPUS AND SOC-XPU PLATFORMS
    2.
    发明申请
    REMOTE STORAGE FOR HARDWARE MICROSERVICES HOSTED ON XPUS AND SOC-XPU PLATFORMS 有权

    公开(公告)号：US20220113911A1

    公开(公告)日：2022-04-14

    申请号：US17558268

    申请日：2021-12-21

    Applicant: Intel Corporation

    Inventor： Andrzej KURIATA ,  Susanne M. BALLE ,  Duane E. GALBI ,  Sundar NADATHUR ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

    IPC: G06F3/06 ,  G06F15/78

    Abstract: Methods, apparatus, and software for remote storage of hardware microservices hosted on other processing units (XPUs) and SOC-XPU Platforms. The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). Software, via execution on the SOC, enables the platform to pre-provision storage space on a remote storage node and assign the storage space to the platform, wherein the pre-provisioned storage space includes one or more container images to be implemented as one or more hardware (HW) microservice front-ends. The XPU/FPGA is configured to implement one or more accelerator functions used to accelerate HW microservice backend operations that are offloaded from the one or more HW microservice front-ends. The platform is also configured to pre-provision a remote storage volume containing worker node components and access and persistently store worker node components.

    MICROSERVICE DATA PATH AND CONTROL PATH PROCESSING
    3.
    发明申请
    MICROSERVICE DATA PATH AND CONTROL PATH PROCESSING 有权

    公开(公告)号：US20220321491A1

    公开(公告)日：2022-10-06

    申请号：US17844506

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Susanne M. BALLE ,  Shihwei CHIEN ,  Duane E. GALBI ,  Nagabhushan CHITLUR

    IPC: H04L47/43 ,  H04L67/133

    Abstract: Examples described herein relate to a network interface device that includes circuitry to process data and circuitry to split a received flow of a mixture of control and data content and provide the control content to a control plane processor and provide the data content for access to the circuitry to process data, wherein the mixture of control and data content are received as part of a Remote Procedure Call. In some examples, provide the control content to a control plane processor, the circuitry is to remove data content from a received packet and include an indicator of a location of removed data content in the received packet.

    TECHNOLOGIES FOR HARDWARE MICROSERVICES ACCELERATED IN XPU
    6.
    发明公开
    TECHNOLOGIES FOR HARDWARE MICROSERVICES ACCELERATED IN XPU 审中-公开

    公开(公告)号：US20230185760A1

    公开(公告)日：2023-06-15

    申请号：US17549727

    申请日：2021-12-13

    Applicant: Intel Corporation

    Inventor： Susanne M. BALLE ,  Duane E. GALBI ,  Andrzej KURIATA ,  Sundar NADATHUR ,  Nagabhushan CHITLUR ,  Francesc GUIM BERNAT ,  Alexander BACHMUTSKY

    IPC: G06F15/78

    CPC classification number: G06F15/7889 ,  G06F15/7821 ,  G06F15/7871 ,  G06F2015/768

    Abstract: Methods, apparatus, and software and for hardware microservices accelerated in other processing units (XPUs). The apparatus may be a platform including a System on Chip (SOC) and an XPU, such as a Field Programmable Gate Array (FPGA). The FPGA is configured to implement one or more Hardware (HW) accelerator functions associated with HW microservices. Execution of microservices is split between a software front-end that executes on the SOC and a hardware backend comprising the HW accelerator functions. The software front-end offloads a portion of a microservice and/or associated workload to the HW microservice backend implemented by the accelerator functions. An XPU or FPGA proxy is used to provide the microservice front-ends with shared access to HW accelerator functions, and schedules/multiplexes access to the HW accelerator functions using, e.g., telemetry data generated by the microservice front-ends and/or the HW accelerator functions. The platform may be an infrastructure processing unit (IPU) configured to accelerate infrastructure operations.

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