公开(公告)号：US20240220445A1

公开(公告)日：2024-07-04

申请号：US18147829

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Kameran Azadet ,  Kevin Kinney ,  Thomas Smith ,  Zoran Zivkovic

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F15/80 ,  G06F9/5027 ,  G06F9/54

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of DPD terms. The architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.

公开(公告)号：US20230205730A1

公开(公告)日：2023-06-29

申请号：US17560637

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Zoran Zivkovic ,  Kameran Azadet ,  Kannan Rajamani ,  Thomas Smith

IPC: G06F15/80 ,  G06F17/11

CPC classification number: G06F15/8092 ,  G06F17/11

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

公开(公告)号：US20230205727A1

公开(公告)日：2023-06-29

申请号：US17560685

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Zoran Zivkovic ,  Kameran Azadet ,  Kannan Rajamani ,  Thomas Smith

IPC: G06F15/80 ,  G06F1/26

CPC classification number: G06F15/80 ,  G06F1/26

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

公开(公告)号：US20240008045A1

公开(公告)日：2024-01-04

申请号：US17853194

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Kannan Rajamani ,  Kameran Azadet ,  Kevin Kinney ,  Thomas Smith ,  Zoran Zivkovic

IPC: H04W72/04 ,  H04J3/06

CPC classification number: H04W72/042 ,  H04J3/0661

Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.