公开(公告)号：US20190042514A1

公开(公告)日：2019-02-07

申请号：US16049607

申请日：2018-07-30

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Sivakumar RADHAKRISHNAN ,  Jayasekhar THOLIYIL ,  Tina C. ZHONG ,  Malay TRIVEDI

IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445 ,  G06F13/16 ,  G06F13/42

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

公开(公告)号：US20210389984A1

公开(公告)日：2021-12-16

申请号：US17410818

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Robert PAWLOWSKI ,  Ankit MORE ,  Jason M. HOWARD ,  Joshua B. FRYMAN ,  Tina C. ZHONG ,  Shaden SMITH ,  Sowmya PITCHAIMOORTHY ,  Samkit JAIN ,  Vincent CAVE ,  Sriram AANANTHAKRISHNAN ,  Bharadwaj KRISHNAMURTHY

IPC: G06F9/48 ,  G06F12/0815 ,  G06F9/35 ,  G06F9/38 ,  G06F13/28 ,  G06F9/30

Abstract: Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.