公开(公告)号：US11646288B2

公开(公告)日：2023-05-09

申请号：US16635146

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Gianni Signorini ,  Veronica Sciriha ,  Thomas Wagner

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/15311 ,  H01L2924/19104

Abstract: In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

公开(公告)号：US11081541B2

公开(公告)日：2021-08-03

申请号：US16881954

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Veronica Sciriha ,  Georg Seidemann

IPC: H01L23/64 ,  H01L49/02 ,  H01L23/522 ,  H01L23/00

Abstract: A system and method of providing a coil in an electronic communication device in is disclosed. Multiple dielectric layers are deposited and patterned on a semiconductor substrate or insulating mold compound. The dielectric layers provide conductive contact with a contact pad on the underlying structure. Shielding for the coil, including a seed layer covered by an insulating material, is disposed in a via of a lowermost of the dielectric layers. Grounding of the shielding seed layer is through a contact pad on the substrate or a trace between the dielectric layers. A coil is fabricated over the shielding and a solder mask deposited and patterned to cover and insulate the coil. The coil is fabricated in a via of a dielectric layer immediately below the solder mask or above this dielectric layer. Electrical contact is provided by multiple copper and seed layers in the solder mask and dielectric layers.