公开(公告)号：US20160173906A1

公开(公告)日：2016-06-16

申请号：US14567162

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： ZHIJUN LEI ,  JASON TANNER

IPC: H04N19/593 ,  H04N19/167 ,  H04N19/96 ,  H04N19/52 ,  H04N19/51 ,  H04N19/61

CPC classification number: H04N19/176 ,  H04N19/119 ,  H04N19/122 ,  H04N19/14 ,  H04N19/192 ,  H04N19/96

Abstract: Techniques related to determining partition modes and transform sizes for video coding are discussed. Such techniques may include determining a portion of a video frame is flat and bypassing an inter-prediction partition check and/or a transform size check for the portion of the video frame based on the portion of the video frame being flat.

Abstract translation: 讨论了与决定分割模式和视频编码变换大小有关的技术。 这样的技术可以包括基于视频帧的平坦部分来确定视频帧的一部分是平坦的并绕过帧间预测分区检查和/或视频帧的部分的变换大小检查。

公开(公告)号：US20220058853A1

公开(公告)日：2022-02-24

申请号：US17500631

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20230360307A1

公开(公告)日：2023-11-09

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US20200051309A1

公开(公告)日：2020-02-13

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T17/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.