公开(公告)号：US20200267394A1

公开(公告)日：2020-08-20

申请号：US16800368

申请日：2020-02-25

Applicant: INTEL CORPORATION

Inventor： JASON TANNER ,  JAY M. PATEL

IPC: H04N19/176 ,  H04N19/192 ,  H04N19/139 ,  H04N19/53 ,  H04N19/523 ,  H04N19/105 ,  H04N19/567

Abstract: Techniques related to video coding with a multi-pass prediction mode decision pipeline.

公开(公告)号：US20160173906A1

公开(公告)日：2016-06-16

申请号：US14567162

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： ZHIJUN LEI ,  JASON TANNER

IPC: H04N19/593 ,  H04N19/167 ,  H04N19/96 ,  H04N19/52 ,  H04N19/51 ,  H04N19/61

CPC classification number: H04N19/176 ,  H04N19/119 ,  H04N19/122 ,  H04N19/14 ,  H04N19/192 ,  H04N19/96

Abstract: Techniques related to determining partition modes and transform sizes for video coding are discussed. Such techniques may include determining a portion of a video frame is flat and bypassing an inter-prediction partition check and/or a transform size check for the portion of the video frame based on the portion of the video frame being flat.

Abstract translation: 讨论了与决定分割模式和视频编码变换大小有关的技术。 这样的技术可以包括基于视频帧的平坦部分来确定视频帧的一部分是平坦的并绕过帧间预测分区检查和/或视频帧的部分的变换大小检查。

公开(公告)号：US20200043190A1

公开(公告)日：2020-02-06

申请号：US16050724

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： JASON TANNER ,  KAI XIAO ,  JILL BOYCE ,  NARAYAN BISWAL ,  JEFFREY TRIPP

IPC: G06T7/593 ,  G06T7/13 ,  G06T7/136 ,  G06T5/00 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first image projection into a plurality of regions, the plurality of regions comprising a plurality of points, determine an accuracy rating for the plurality of regions, and apply one of a first rendering technique to a first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions fails to meet an accuracy threshold or a second rendering technique to the first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions meets an accuracy threshold, and a memory communicatively coupled to the processor. Other embodiments may be described and claimed.

公开(公告)号：US20200043122A1

公开(公告)日：2020-02-06

申请号：US16050595

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： KAI XIAO ,  GOKCEN CILINGIR ,  JASON TANNER ,  SANG-HEE LEE ,  ATSUO KUWAHARA

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06F17/18

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first projection into a plurality of regions, the plurality of regions comprising a plurality of pixels, detect errant visual content in a first region in the plurality of regions, determine a detail frequency rating for the first region, and apply one of a first rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions fails to meet a detail frequency threshold or a second rendering technique to the first region in the plurality of regions when the detail frequency rating for the first region in the plurality of regions meets a detail frequency threshold. Other embodiments may be described and claimed.

公开(公告)号：US20180293965A1

公开(公告)日：2018-10-11

申请号：US15482535

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  JASON TANNER ,  JOYDEEP RAY ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K

IPC: G09G5/395 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00 ,  H04N19/42 ,  G06T1/20 ,  G06T9/00

CPC classification number: G09G5/395 ,  G06F3/1423 ,  G06F9/452 ,  G06F9/45533 ,  G06T1/20 ,  G06T1/60 ,  G06T9/004 ,  G06T15/005 ,  G09G3/003 ,  G09G5/36 ,  G09G5/363 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2370/022 ,  H04N19/42

Abstract: An apparatus and method are described for efficiently rendering an transmitting to a remote display. For example, one embodiment of a remote display apparatus comprises: a display engine to render a sequence of video images; an encoder to compress the sequence of video images to generate a sequence of compressed video images; a network interface controller to transmit the compressed video images over a network link to a remote display; a plurality of buffer pointer registers to store read pointers and write pointers identifying read locations and write locations, respectively, in a frame buffer and a compressed stream buffer; a central processing unit (CPU) to initialize the read pointers and write pointers for processing one or more of the video images; and the display engine to access a first write pointer to write to a specified location in the frame buffer, the encoder to begin reading from the frame buffer based on a first read pointer value, the encoder to write to the compressed stream buffer based on a second write pointer value, and the network interface controller to read from the compressed stream buffer based on a second read pointer value, the first and second write and read pointer values to be updated without intervention from the CPU as the display engine writes to the frame buffer, the encoder reads from the frame buffer and writes to the compressed stream buffer, and the network interface controller reads from the compressed stream buffer.

公开(公告)号：US20200043217A1

公开(公告)日：2020-02-06

申请号：US16050375

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： GOKCEN CILINGIR ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JAMES HOLLAND ,  SANG-HEE LEE ,  JASON TANNER ,  MAYURESH VARERKAR ,  KAI XIAO

IPC: G06T15/00 ,  G06T9/00 ,  H04N19/597

Abstract: A mechanism is described for facilitating enhanced immersive media pipeline for correction of artifacts and clarity of objects in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to extract semantic data relating to objects in a scene captured through one or more cameras, where the objects include distortions, and form, based on the semantic data, a three-dimensional (3D) model of contents of the scene, where the contents include the objects. The one or more processors are further to encode the 3D model including the contents and the semantic data into an encoded file having encoded contents and encoded semantic data and transmit the encoded file over an immersive media pipeline to facilitate correction of the distortions and rendering the scene including the objects without the distortions.

公开(公告)号：US20170324973A1

公开(公告)日：2017-11-09

申请号：US15147043

申请日：2016-05-05

Applicant: INTEL CORPORATION

Inventor： JASON TANNER ,  JAY PATEL

IPC: H04N19/513 ,  H04N19/172 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/176 ,  H04N19/105 ,  H04N19/139 ,  H04N19/192 ,  H04N19/523 ,  H04N19/53 ,  H04N19/567

Abstract: Techniques related to video coding with a multi-pass prediction mode decision pipeline.

公开(公告)号：US20170322612A1

公开(公告)日：2017-11-09

申请号：US15148115

申请日：2016-05-06

Applicant: Intel Corporation

Inventor： MARC BEUCHAT ,  JASON TANNER

IPC: G06F1/32 ,  G06T1/20

CPC classification number: G06F1/324 ,  G06F1/3228 ,  G06F1/3243 ,  G06T1/20

Abstract: One embodiment provides an apparatus. The apparatus includes a graphics processor and power management logic. The graphics processor includes display engine logic and encoder logic. The power management logic is to adjust an operating frequency of the encoder logic based, at least in part, on an encode time duration and based, at least in part, on a frame period.