公开(公告)号：US20230186545A1

公开(公告)日：2023-06-15

申请号：US17551647

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss ,  Rajabali Koduri

IPC: G06T15/00 ,  G06T15/20 ,  G06T1/20 ,  H04N19/597 ,  G06T15/04

CPC classification number: G06T15/005 ,  G06T15/20 ,  G06T1/20 ,  H04N19/597 ,  G06T15/04

Abstract: Described herein is a cloud-based gaming system in which multiple views of a spectated E-sports event can be rendered and combined into an immersive video having at least three degrees of freedom. Low-latency generation of the immersive video is facilitated via the use of GPU-controlled non-volatile memory on which rendered data for multiple viewpoints are stored.

公开(公告)号：US11443406B2

公开(公告)日：2022-09-13

申请号：US17323818

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06N20/00 ,  G06N3/08 ,  G06T1/60 ,  G06F9/46

Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.

公开(公告)号：US20220101597A1

公开(公告)日：2022-03-31

申请号：US17032348

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06T15/00 ,  G06T15/10 ,  G06N3/08

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US11037269B1

公开(公告)日：2021-06-15

申请号：US16832996

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/46 ,  G06F9/50 ,  G06N3/08 ,  G06N20/00

Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.

公开(公告)号：US11978155B2

公开(公告)日：2024-05-07

申请号：US17032348

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

CPC classification number: G06T15/80 ,  G06N3/08 ,  G06T15/005 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US11710269B2

公开(公告)日：2023-07-25

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/40 ,  G06T15/80 ,  G06T2210/52

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US10997771B2

公开(公告)日：2021-05-04

申请号：US16116158

申请日：2018-08-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US10733692B2

公开(公告)日：2020-08-04

申请号：US16185988

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Slawomir Grajewski ,  Jason Surprise ,  Zack Waters ,  Mike Apodaca

IPC: G06T1/60 ,  G06T1/20

Abstract: Apparatus and method for resilient interface for updating a graphics processor. For example, one embodiment of an apparatus comprises a graphics processor; and a configuration memory of the graphics processor to be subdivided into a plurality of configuration regions associated with a corresponding plurality of graphics pipeline stages and/or functional units, wherein a host processor executing a graphics driver is to submit a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of the configuration memory and configuration data to be used to modify at least one configuration region associated with the at least one logical memory address, and wherein the logical memory address is to be used to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units, the at least one configuration region to be responsively updated.

公开(公告)号：US20240303915A1

公开(公告)日：2024-09-12

申请号：US18610369

申请日：2024-03-20

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  Carl S. Marshall ,  Ravishankar Iyer ,  Zack Waters

IPC: G06T15/80 ,  G06N3/08 ,  G06T15/00 ,  G06T15/10

CPC classification number: G06T15/80 ,  G06N3/08 ,  G06T15/005 ,  G06T15/10

Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

公开(公告)号：US20210304351A1

公开(公告)日：2021-09-30

申请号：US17323818

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Charles Moidel ,  Michael Apodaca ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06N20/00 ,  G06N3/08 ,  G06T1/60 ,  G06F9/46

Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.