公开(公告)号：US10733693B2

公开(公告)日：2020-08-04

申请号：US16208715

申请日：2018-12-04

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Jason Surprise ,  Peter Doyle

IPC: G06T15/10 ,  G06T1/20 ,  G06F9/50

Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.

公开(公告)号：US11710269B2

公开(公告)日：2023-07-25

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/40 ,  G06T15/80 ,  G06T2210/52

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US10997771B2

公开(公告)日：2021-05-04

申请号：US16116158

申请日：2018-08-29

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US10733692B2

公开(公告)日：2020-08-04

申请号：US16185988

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Slawomir Grajewski ,  Jason Surprise ,  Zack Waters ,  Mike Apodaca

IPC: G06T1/60 ,  G06T1/20

Abstract: Apparatus and method for resilient interface for updating a graphics processor. For example, one embodiment of an apparatus comprises a graphics processor; and a configuration memory of the graphics processor to be subdivided into a plurality of configuration regions associated with a corresponding plurality of graphics pipeline stages and/or functional units, wherein a host processor executing a graphics driver is to submit a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of the configuration memory and configuration data to be used to modify at least one configuration region associated with the at least one logical memory address, and wherein the logical memory address is to be used to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units, the at least one configuration region to be responsively updated.