公开(公告)号：US20140098592A1

公开(公告)日：2014-04-10

申请号：US14047537

申请日：2013-10-07

Applicant: JAE-KYU LEE

Inventor： JAE-KYU LEE

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C5/04 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/0433 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/79

Abstract: A resistive memory device includes a memory cell array, an input/output (I/O) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device. The I/O sense amplifier unit amplifies data output from the memory cell array to generate first data, and transfers input data to the memory cell array. The address input buffer generates a row address signal and a column address signal based on an external address. The row decoder decodes the row address signal and generates the word line driving signal based on the decoded row address signal. The column decoder decodes the column address signal and generates the column selecting signal based on the decoded column address signal.

Abstract translation: 电阻式存储器件包括存储单元阵列，输入/输出（I / O）读出放大器单元，地址输入缓冲器，行解码器和列译码器。 存储单元阵列包括单元存储单元，并且响应于字线驱动信号和列选择信号而工作，每个单元存储单元包括电阻器件和补偿电阻器件。 I / O读出放大器单元放大从存储单元阵列输出的数据以产生第一数据，并将输入数据传送到存储单元阵列。 地址输入缓冲器基于外部地址生成行地址信号和列地址信号。 行解码器解码行地址信号，并基于解码的行地址信号产生字线驱动信号。 列解码器解码列地址信号，并根据解码的列地址信号产生列选择信号。