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公开(公告)号：US06724603B2
公开(公告)日：2004-04-20
申请号：US10216336
申请日：2002-08-09
申请人： James W. Miller , Geoffrey B. Hall , Alexander Krasin , Michael Stockinger , Matthew D Akers , Vishnu G. Kamat
发明人： James W. Miller , Geoffrey B. Hall , Alexander Krasin , Michael Stockinger , Matthew D Akers , Vishnu G. Kamat
IPC分类号： H02H322
CPC分类号： H01L27/0292 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.
摘要翻译： 静电放电（ESD）保护电路（9）包括多个I / O和电源焊盘单元（22,40），其包括外部焊盘（31,41）和需要ESD保护的电路。 保护电路包括并联在ESD总线（14）和VSS总线（18）之间并分布在多个焊盘单元之间的分流器件阵列（36,46）。 一个或多个触发电路（50）控制分流装置。 ESD事件从任何应力焊盘耦合到两个单独的总线上：将高ESD电流路由到多个分流装置的正电流电极的ESD总线以及控制触发电路的升压总线（12）。 在ESD事件期间，触发电路将分流装置的控制电极驱动到比现有技术电路更可能的电压电平，从而降低分流装置的导通电阻。
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2.发明授权Distributed electrostatic discharge protection circuit with varying clamp size 有权具有不同钳位尺寸的分布式静电放电保护电路公开(公告)号：US07589945B2
公开(公告)日：2009-09-15
申请号：US11513638
申请日：2006-08-31
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。
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公开(公告)号：US07236339B2
公开(公告)日：2007-06-26
申请号：US11111528
申请日：2005-04-21
IPC分类号： H02H9/00
CPC分类号： H01L27/0277
摘要： An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).
摘要翻译： 提供ESD保护电路（81）和提供ESD保护的方法。 在一些实施例中，可以被ESD损坏的N沟道晶体管（24）选择性地导通并导通。 打开N沟道晶体管（24）的目的是使N沟道晶体管（24）的Vt1最大化。 Vt1是首先发生N沟道晶体管（24）的寄生双极作用的漏极到源极电压点。 在一些实施例中，ESD保护电路（81）包括提供从I / O焊盘31到第一电源节点（76）的附加电流路径的二极管（64）。
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公开(公告)号：US06879476B2
公开(公告)日：2005-04-12
申请号：US10348814
申请日：2003-01-22
IPC分类号： H01L20060101 , H01L23/62 , H01L27/02 , H01L27/04 , H02H1/04 , H02H3/00 , H02H3/20 , H02H3/22 , H02H7/00 , H02H9/00 , H02H9/06
CPC分类号： H01L27/0277 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).
摘要翻译： 提供ESD保护电路（81）和提供ESD保护的方法。 在一些实施例中，可以被ESD损坏的N沟道晶体管（24）选择性地导通并导通。 打开N沟道晶体管（24）的目的是使N沟道晶体管（24）的Vt1最大化。 Vt1是首先发生N沟道晶体管（24）的寄生双极作用的漏极到源极电压点。 在一些实施例中，ESD保护电路（81）包括提供从I / O焊盘31到第一电源节点（76）的附加电流路径的二极管（64）。
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公开(公告)号：US07446990B2
公开(公告)日：2008-11-04
申请号：US11056617
申请日：2005-02-11
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.
摘要翻译： 集成电路的I / O单元的ESD保护系统。 一组单元的I / O单元包括具有ESD触发电路的第一类型的I / O单元和具有ESD钳位装置的第二类型的I / O单元。 在一个实施例中，第一类型的ESD触发电路位于与第二类型的I / O单元的ESD钳位装置的平面图中的区域有关的电路平面图的相同区域。
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公开(公告)号：US07209332B2
公开(公告)日：2007-04-24
申请号：US10315796
申请日：2002-12-10
IPC分类号： H02H3/20
CPC分类号： H01L27/0285 , H01L27/0251 , H01L2924/0002 , H03K17/223 , H01L2924/00
摘要： A transient detection circuit which may be used in an electrostatic discharge (ESD) clamp circuit. The transient detection circuit includes a filter circuit and an inverter circuit. The voltage switch point of the inverter circuit has a constant voltage offset from one of the nodes. When a filtered voltage level from the filter circuit crosses the voltage switch point of the inverter circuit (indicative of an ESD event), the inverter circuit provides a signal indicating an ESD event.
摘要翻译： 可用于静电放电（ESD）钳位电路的瞬态检测电路。 瞬态检测电路包括滤波电路和反相器电路。 逆变器电路的电压切换点与其中一个节点具有恒定的电压偏移。 当来自滤波器电路的滤波电压电平与逆变器电路的电压切换点（表示ESD事件）相交时，逆变器电路提供指示ESD事件的信号。
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公开(公告)号：US06900970B2
公开(公告)日：2005-05-31
申请号：US10348939
申请日：2003-01-22
CPC分类号： H01L27/0277
摘要： An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).
摘要翻译： 提供ESD保护电路（81）和提供ESD保护的方法。 在一些实施例中，可以被ESD损坏的N沟道晶体管（24）选择性地导通并导通。 打开N沟道晶体管（24）的目的是使N沟道晶体管（24）的Vt1最大化。 Vt1是首先发生N沟道晶体管（24）的寄生双极作用的漏极到源极电压点。 在一些实施例中，ESD保护电路（81）包括提供从I / O焊盘31到第一电源节点（76）的附加电流路径的二极管（64）。
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8.发明申请Distributed electrostatic discharge protection circuit with varying clamp size 有权具有不同钳位尺寸的分布式静电放电保护电路公开(公告)号：US20080062596A1
公开(公告)日：2008-03-13
申请号：US11513638
申请日：2006-08-31
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。
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公开(公告)号：US06970336B2
公开(公告)日：2005-11-29
申请号：US10684112
申请日：2003-10-10
CPC分类号： H01L27/0251 , H01L27/0292 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit (201) is for use with a high-voltage tolerant I/O circuit in an IC. This is accomplished by providing a small ESD diode (217) from the I/O pad to a relatively small boosted voltage bus (BOOST BUS). The BOOST BUS is used to power a trigger circuit (203). This path has very little current flow during an ESD event due to minimal current dissipation in the trigger circuit. There is a diode drop but only very little IR voltage drop from the I/O pad to the trigger circuit (203). The trigger circuit (203) controls relatively large cascoded clamp NMOSFETs (207, 209). The net result is that a gate-to-source voltage (VGS) of both of the clamp NMOSFETs is increased thus increasing the conductivity of the cascoded clamp NMOSFETs (207, 209). This reduces the on-resistance of each of the NMOSFETS (207, 209), thereby improving the ESD performance, and reducing the layout area required to implement robust ESD protection circuits.
摘要翻译： ESD保护电路（201）用于IC中的高耐压I / O电路。 这是通过从I / O焊盘到相对较小的升压电压总线（BOOST BUS）提供一个小型ESD二极管（217）来实现的。 BOOST BUS用于为触发电路（203）供电。 由于触发电路中的电流消耗最小，因此在ESD事件期间该路径具有非常小的电流。 存在二极管压降，但是从I / O焊盘到触发电路（203）仅有很少的IR电压降。 触发电路（203）控制相对较大的级联钳位NMOSFET（207,209）。 最终的结果是两个钳位NMOSFET的栅极 - 源极电压（VGS）增加，从而增加了级联钳位NMOSFET（207,209）的电导率。 这降低了每个NMOSFET（207,209）的导通电阻，从而提高了ESD性能，并且减少了实现鲁棒ESD保护电路所需的布局面积。
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公开(公告)号：US20050078419A1
公开(公告)日：2005-04-14
申请号：US10684112
申请日：2003-10-10
申请人： Michael Stockinger , James Miller
发明人： Michael Stockinger , James Miller
CPC分类号： H01L27/0251 , H01L27/0292 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit (201) is for use with a high-voltage tolerant I/O circuit in an IC. This is accomplished by providing a small ESD diode (217) from the I/O pad to a relatively small boosted voltage bus (BOOST BUS). The BOOST BUS is used to power a trigger circuit (203). This path has very little current flow during an ESD event due to minimal current dissipation in the trigger circuit. There is a diode drop but only very little IR voltage drop from the I/O pad to the trigger circuit (203). The trigger circuit (203) controls relatively large cascoded clamp NMOSFETs (207, 209). The net result is that a gate-to-source voltage (VGS) of both of the clamp NMOSFETs is increased thus increasing the conductivity of the cascoded clamp NMOSFETs (207, 209). This reduces the on-resistance of each of the NMOSFETS (207, 209), thereby improving the ESD performance, and reducing the layout area required to implement robust ESD protection circuits.
摘要翻译： ESD保护电路（201）用于IC中的耐高压I / O电路。 这是通过从I / O焊盘到相对较小的升压电压总线（BOOST BUS）提供一个小型ESD二极管（217）来实现的。 BOOST BUS用于为触发电路（203）供电。 由于触发电路中的电流消耗最小，因此在ESD事件期间该路径具有非常小的电流。 存在二极管压降，但是从I / O焊盘到触发电路（203）仅有很少的IR电压降。 触发电路（203）控制相对较大的级联钳位NMOSFET（207,209）。 最终的结果是两个钳位NMOSFET的栅极 - 源极电压（VGS）增加，从而增加了级联钳位NMOSFET（207,209）的电导率。 这降低了每个NMOSFET（207,209）的导通电阻，从而提高了ESD性能，并且减少了实现鲁棒ESD保护电路所需的布局面积。
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