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1.发明授权Distributed electrostatic discharge protection circuit with varying clamp size 有权具有不同钳位尺寸的分布式静电放电保护电路公开(公告)号：US07589945B2
公开(公告)日：2009-09-15
申请号：US11513638
申请日：2006-08-31
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。
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2.发明申请Distributed electrostatic discharge protection circuit with varying clamp size 有权具有不同钳位尺寸的分布式静电放电保护电路公开(公告)号：US20080062596A1
公开(公告)日：2008-03-13
申请号：US11513638
申请日：2006-08-31
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.
摘要翻译： 集成电路包括设置在基板上的第一I / O单元，第一I / O单元包括第一静电放电（ESD）钳位晶体管器件。 第一ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第一ESD钳位晶体管器件具有第一通道宽度。 集成电路还包括具有第二ESD钳位晶体管器件的第二I / O单元。 第二ESD钳位晶体管器件包括控制电极，耦合到第一电压参考总线的第一电流电极和耦合到第二电压参考总线的第二电流电极。 第二ESD钳位晶体管器件具有与第一通道宽度不同的第二通道宽度。
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公开(公告)号：US07446990B2
公开(公告)日：2008-11-04
申请号：US11056617
申请日：2005-02-11
IPC分类号： H02H9/00
CPC分类号： H01L27/0251 , H01L27/0292
摘要： An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.
摘要翻译： 集成电路的I / O单元的ESD保护系统。 一组单元的I / O单元包括具有ESD触发电路的第一类型的I / O单元和具有ESD钳位装置的第二类型的I / O单元。 在一个实施例中，第一类型的ESD触发电路位于与第二类型的I / O单元的ESD钳位装置的平面图中的区域有关的电路平面图的相同区域。
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公开(公告)号：US06900970B2
公开(公告)日：2005-05-31
申请号：US10348939
申请日：2003-01-22
CPC分类号： H01L27/0277
摘要： An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).
摘要翻译： 提供ESD保护电路（81）和提供ESD保护的方法。 在一些实施例中，可以被ESD损坏的N沟道晶体管（24）选择性地导通并导通。 打开N沟道晶体管（24）的目的是使N沟道晶体管（24）的Vt1最大化。 Vt1是首先发生N沟道晶体管（24）的寄生双极作用的漏极到源极电压点。 在一些实施例中，ESD保护电路（81）包括提供从I / O焊盘31到第一电源节点（76）的附加电流路径的二极管（64）。
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公开(公告)号：US06879476B2
公开(公告)日：2005-04-12
申请号：US10348814
申请日：2003-01-22
IPC分类号： H01L20060101 , H01L23/62 , H01L27/02 , H01L27/04 , H02H1/04 , H02H3/00 , H02H3/20 , H02H3/22 , H02H7/00 , H02H9/00 , H02H9/06
CPC分类号： H01L27/0277 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).
摘要翻译： 提供ESD保护电路（81）和提供ESD保护的方法。 在一些实施例中，可以被ESD损坏的N沟道晶体管（24）选择性地导通并导通。 打开N沟道晶体管（24）的目的是使N沟道晶体管（24）的Vt1最大化。 Vt1是首先发生N沟道晶体管（24）的寄生双极作用的漏极到源极电压点。 在一些实施例中，ESD保护电路（81）包括提供从I / O焊盘31到第一电源节点（76）的附加电流路径的二极管（64）。
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公开(公告)号：US07236339B2
公开(公告)日：2007-06-26
申请号：US11111528
申请日：2005-04-21
IPC分类号： H02H9/00
CPC分类号： H01L27/0277
摘要： An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).
摘要翻译： 提供ESD保护电路（81）和提供ESD保护的方法。 在一些实施例中，可以被ESD损坏的N沟道晶体管（24）选择性地导通并导通。 打开N沟道晶体管（24）的目的是使N沟道晶体管（24）的Vt1最大化。 Vt1是首先发生N沟道晶体管（24）的寄生双极作用的漏极到源极电压点。 在一些实施例中，ESD保护电路（81）包括提供从I / O焊盘31到第一电源节点（76）的附加电流路径的二极管（64）。
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公开(公告)号：US20090310266A1
公开(公告)日：2009-12-17
申请号：US12139106
申请日：2008-06-13
CPC分类号： G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.
摘要翻译： eFuse（电子熔断器）电路具有用于确定在集成电路的电路板处是否发生ESD（静电放电）事件的第一检测器，并响应于此提供ESD触发信号。 第二检测器检测第一电源电压的存在并提供指示第一电源电压的存在的上电信号。 当不发生ESD事件检测时，保险丝被允许可编程，同时检测到通电信号的存在。 当检测到ESD事件或没有通电信号时，不允许对熔丝进行编程。 因此，保险丝阵列可以防止意外编程从ESD事件或加电集成电路。
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公开(公告)号：US08009397B2
公开(公告)日：2011-08-30
申请号：US12139106
申请日：2008-06-13
IPC分类号： H02H9/00
CPC分类号： G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.
摘要翻译： eFuse（电子熔断器）电路具有用于确定在集成电路的电路板处是否发生ESD（静电放电）事件的第一检测器，并响应于此提供ESD触发信号。 第二检测器检测第一电源电压的存在并提供指示第一电源电压的存在的上电信号。 当不发生ESD事件检测时，保险丝被允许可编程，同时检测到通电信号的存在。 当检测到ESD事件或没有通电信号时，不允许对熔丝进行编程。 因此，保险丝阵列可以防止意外编程从ESD事件或加电集成电路。
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公开(公告)号：US06500723B1
公开(公告)日：2002-12-31
申请号：US09972397
申请日：2001-10-05
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/2253 , H01L21/266 , H01L21/74 , H01L27/0288 , H01L27/0802 , Y10S438/947
摘要： A number of small wells under the isolation layer are formed using the same mask made of photoresist and implant step that is used for the regular wells. The small wells are formed close enough together so that they merge during normal subsequent semiconductor processing to form a merged well. The normal wells and the small wells have a concentration that is greater than that of the merged well. The desired merging of the small wells is ensured by making sure that the small wells are sufficiently close together that the normal diffusion of well implants, which occurs from the particular semiconductor process that is being used, results in the merging. One desirable use of the merged well, with its lower doping concentration, is as a resistor that has more resistance than that of the regular well without requiring an additional implant.
摘要翻译： 使用与用于常规孔的光致抗蚀剂和植入步骤相同的掩模形成隔离层下面的许多小孔。 小孔形成得足够接近，使得它们在正常的后续半导体处理期间合并以形成合并井。 正常井和小井的浓度大于合并井的浓度。 通过确保小井足够靠近，使得从正在使用的特定半导体工艺发生的井注入的正常扩散导致合并，确保小井的期望合并。 与掺杂浓度较低的合并井的一个理想用途是作为电阻器，具有比常规阱更多的电阻，而不需要额外的注入。
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公开(公告)号：US06327126B1
公开(公告)日：2001-12-04
申请号：US09494055
申请日：2000-01-28
申请人： James W. Miller , Michael G. Khazhinsky , Geoffrey B. Hall , Jose A. Camarena , Joseph Chan , Fujio Takeda
发明人： James W. Miller , Michael G. Khazhinsky , Geoffrey B. Hall , Jose A. Camarena , Joseph Chan , Fujio Takeda
IPC分类号： H02H900
CPC分类号： H01L27/0251
摘要： A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately ½ of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.
摘要翻译： 电路（600）在ESD事件期间为集成电路中的内部元件提供静电放电（ESD）保护。 电路（600）包括级联的NMOSFET（614,616），其中上部NMOSFET（614）连接到分压器电路（628）。 分压器电路（628）在ESD事件期间向上NMOSFET（614）的栅极提供第一偏置电压，并在正常操作期间提供第二偏置电压。 优选地，第一偏置电压约为上部NMOSFET（614）的漏极电压的1/2。 在这些偏置条件下，级联的NMOSFET表现出用于启动寄生横向双极传导的最大电压阈值。
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