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公开(公告)号：US06934656B2
公开(公告)日：2005-08-23
申请号：US10605884
申请日：2003-11-04
CPC分类号： G06F11/261
摘要： A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.
摘要翻译： 用于识别构成虚拟机的逻辑功能区域受到特定测试用例影响的方法和系统。 硬件描述符语言（HDL）用于创建虚拟机的软件模型。 模拟器编译和分析HDL模型，并创建一个标识虚拟机中逻辑功能区域的矩阵记分板。 测试用例的完整列表在虚拟机上运行，而监视器将每个测试用例与受影响的逻辑功能区域相关联，以填充矩阵记分板。 当随后的测试失败发生时，由于对逻辑功能区域的修改或新测试的执行，所有被直接或间接影响的逻辑功能区域都被识别。
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2.发明申请公开(公告)号：US20090138676A1
公开(公告)日：2009-05-28
申请号：US11946096
申请日：2007-11-28
CPC分类号： G06F1/06 , G06F1/08 , G06F9/3869
摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。
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3.发明授权Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers 失效数字系统噪声降低时，噪声是由数据寄存器同步引起的公开(公告)号：US07463083B2
公开(公告)日：2008-12-09
申请号：US11937559
申请日：2007-11-09
IPC分类号： H03K5/00
CPC分类号： G06F1/04 , H03K5/1504 , H03K19/00361
摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。
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公开(公告)号：US08037337B2
公开(公告)日：2011-10-11
申请号：US11946096
申请日：2007-11-28
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , G06F1/08 , G06F9/3869
摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。
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公开(公告)号：US07317348B2
公开(公告)日：2008-01-08
申请号：US11275773
申请日：2006-01-27
IPC分类号： H03K5/00
CPC分类号： G06F1/04 , H03K5/1504 , H03K19/00361
摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。
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6.发明授权公开(公告)号：US07873961B2
公开(公告)日：2011-01-18
申请号：US11161330
申请日：2005-07-29
CPC分类号： G06F9/462 , G06F9/4843
摘要： A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.
摘要翻译： 一种用于在单个集成电路上支持同时操作操作系统的方法和系统。 该系统包括管理指令的执行的监控操作系统（SOS），每个指令可在一个操作系统下执行; 寄存器分组成多组寄存器，每组寄存器保持一个操作系统的标识; 以及能够分派指令和附加到指令的标签的调度器，识别操作系统之一的标签和在所识别的操作系统下执行的指令以访问寄存器之一。 当执行指令时，使用一个或多个寄存器，并且被包括在多组寄存器的单组中。 单一集合维护由标签识别的操作系统的标识，并且一个或多个寄存器中的每一个包括与标签相匹配的标识符。
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7.发明申请High Bandwidth Low-Latency Semaphore Mapped Protocol (SMP) For Multi-Core Systems On Chips 失效用于芯片上的多核系统的高带宽低延迟信号量映射协议（SMP）公开(公告)号：US20080229006A1
公开(公告)日：2008-09-18
申请号：US11684687
申请日：2007-03-12
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/544 , G06F15/167
摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.
摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。
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8.发明授权High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips 失效用于芯片上多核系统的高带宽低延迟信号量映射协议（SMP）公开(公告)号：US07765351B2
公开(公告)日：2010-07-27
申请号：US11684687
申请日：2007-03-12
IPC分类号： G06F12/00
CPC分类号： G06F9/526 , G06F9/544 , G06F15/167
摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.
摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。
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9.发明申请Design Structure for Localized Control Caching Resulting in Power Efficient Control Logic 审中-公开用于本地化控制缓存的设计结构，从而产生高效的控制逻辑公开(公告)号：US20080229074A1
公开(公告)日：2008-09-18
申请号：US12127860
申请日：2008-05-28
IPC分类号： G06F9/30
CPC分类号： G06F9/381 , G06F9/3867
摘要： A design structure for an integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.
摘要翻译： 一种用于集成电路（IC）的设计结构，包括解码指令，存储指令作为局部回路的阴影锁存器，以及控制解码器和多个阴影锁存器的状态机。 当状态机识别与存储在本地化环路中的指令相同的指令时，其取消对解码器的激活，并激活多个阴影锁存器来取代并执行本地化的循环，代替解码器提供的指令。 另外，提供了一种在IC中提供局部控制高速缓存操作以减少功耗的方法。 该方法包括初始化状态机以控制IC，提供多个阴影锁存器，解码一组指令，检测解码指令的循环，将阴影锁存器中的解码指令的循环缓存为局部循环，检测循环 循环结束信号，并停止局部循环的缓存。
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10.发明申请公开(公告)号：US20070294519A1
公开(公告)日：2007-12-20
申请号：US11424943
申请日：2006-06-19
IPC分类号： G06F9/44
CPC分类号： G06F9/325 , G06F9/3808 , G06F9/381
摘要： An integrated circuit (IC) including a decoder decoding instructions, shadow latches storing instructions as a localized loop, and a state machine controlling the decoder and the plurality of shadow latches. When the state machine identifies instructions that are the same as those stored in the localized loop, it deactivates the decoder and activates the plurality of shadow latches to retrieve and execute the localized loop in place of the instructions provided by the decoder. Additionally, a method of providing localized control caching operations in an IC to reduce power dissipation is provided. The method includes initializing a state machine to control the IC, providing a plurality of shadow latches, decoding a set of instructions, detecting a loop of decoded instructions, caching the loop of decoded instructions in the shadow latches as a localized loop, detecting a loop end signal for the loop and stopping the caching of the localized loop.
摘要翻译： 包括解码指令，存储指令作为局部回路的阴影锁存器的集成电路（IC）以及控制解码器和多个阴影锁存器的状态机。 当状态机识别与存储在本地化环路中的指令相同的指令时，其取消对解码器的激活，并激活多个阴影锁存器来取代并执行本地化的循环，代替解码器提供的指令。 另外，提供了一种在IC中提供局部控制高速缓存操作以减少功耗的方法。 该方法包括初始化状态机以控制IC，提供多个阴影锁存器，解码一组指令，检测解码指令的循环，将阴影锁存器中的解码指令的循环缓存为局部循环，检测循环 循环结束信号，并停止局部循环的缓存。
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