公开(公告)号：US20060056261A1

公开(公告)日：2006-03-16

申请号：US11008586

申请日：2004-12-09

Applicant: Sebastien Zink ,  Paola Cavaleri ,  Bruno Leconte ,  Jean Devin ,  Francois Maugain

Inventor： Sebastien Zink ,  Paola Cavaleri ,  Bruno Leconte ,  Jean Devin ,  Francois Maugain

IPC: G11C8/00

CPC classification number: G11C8/12 ,  G11C8/04

Abstract: The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocated to the memory within an extended memory array addressable with an extended address of N+K bits, an extended address counter for storing an extended address received at the serial input/output of the memory, the extended address comprising N least significant bits that are applied to the integrated memory array, and K most significant bits, means for comparing the K most significant bits with the most significant address allocated to the memory, and means for preventing the execution of a command for reading or writing the integrated memory array if the K most significant address bits are different to the most significant address allocated to the memory. In one embodiment, a ready/busy pad is provided that is taken to a selected potential to prevent access to the memory.

Abstract translation: 本发明涉及硅微芯片上的存储器，包括串行输入/输出和可在N位下寻址的集成存储器阵列。 根据本发明，存储器包括用于存储可扩展存储器阵列中分配给存储器的最高有效地址的装置，可扩展地址为N + K位，扩展地址计数器用于存储在串行输入端处接收的扩展地址 存储器的输出，包括施加到集成存储器阵列的N个最低有效位的扩展地址和K个最高有效位，用于将K个最高有效位与分配给存储器的最高有效位进行比较的装置，以及用于 如果K个最高有效地址位与分配给存储器的最高有效地址不同，则阻止执行用于读取或写入集成存储器阵列的命令。 在一个实施例中，提供了一个就绪/忙碌垫，其被采取到选择的潜力以防止对存储器的访问。

公开(公告)号：US06714453B2

公开(公告)日：2004-03-30

申请号：US10352581

申请日：2003-01-28

Applicant: Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

Inventor： Paola Cavaleri ,  Bruno Leconte ,  Sebastien Zink ,  Jean Devin

IPC: G11C1604

CPC classification number: G11C16/3418 ,  G11C16/10

Abstract: A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.

Abstract translation: 可由页面擦除的闪速存储器包括包含以页面排列的多个浮置栅极晶体管的闪存阵列，以及用于检查浮置栅极晶体管的阈值电压的检查电路。 具有小于给定阈值的阈值电压的编程晶体管被重新编程。 检查电路包括由至少一行浮动栅极晶体管形成的非易失性计数器，用于读取计数器中要检查的页面的地址的读取电路和用于在页面已经被加载之后递增计数器的递增电路 检查。

公开(公告)号：US06411544B1

公开(公告)日：2002-06-25

申请号：US09590151

申请日：2000-06-08

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C1604

CPC classification number: G11C16/225 ,  G11C16/12

Abstract: A circuit to detect and record the occurrence of a surge in the supply voltage applied to an integrated circuit includes a detection circuit for providing a control signal if a voltage surge is detected. The circuit also includes a high voltage circuit, which produces a high programming voltage from the supply voltage if a voltage surge is detected, and a memory cell. The detection circuit may include a capacitor divider bridge, a voltage source, and a comparator. The circuit is particularly advantageous for use with electrically programmable memories.

Abstract translation: 用于检测和记录施加到集成电路的电源电压中的浪涌的发生的电路包括检测电路，用于在检测到电压浪涌时提供控制信号。 电路还包括高压电路，如果检测到电压浪涌，其产生来自电源电压的高编程电压，以及存储器单元。 检测电路可以包括电容分压器桥，电压源和比较器。 该电路特别有利于与电可编程存储器一起使用。

公开(公告)号：US06279068B1

公开(公告)日：2001-08-21

申请号：US09746472

申请日：2000-12-21

Applicant: Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

Inventor： Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

IPC: G06F1200

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

公开(公告)号：US06205512B1

公开(公告)日：2001-03-20

申请号：US09056921

申请日：1998-04-08

Applicant: Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

Inventor： Alessandro Brigati ,  Jean Devin ,  Bruno Leconte

IPC: G06F1200

CPC classification number: G11C8/12 ,  G11C7/00

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

公开(公告)号：US5303189A

公开(公告)日：1994-04-12

申请号：US663410

申请日：1991-03-01

Applicant: Jean Devin ,  Emilio Yero ,  Claude Costabello

Inventor： Jean Devin ,  Emilio Yero ,  Claude Costabello

IPC: G11C7/12 ,  G11C16/24 ,  G11C16/26 ,  G11C11/34

CPC classification number: G11C16/24 ,  G11C16/26 ,  G11C7/12

Abstract: An erasable and electrically programmable memory with only few cells works at high speed in reading mode and is reliable. This is achieved by using a voltage limiter that limits the variation in the drain voltage of the memory cells.

Abstract translation: 一个可擦除和电可编程的存储器，只有少量单元在读取模式下以高速工作，并且可靠。 这通过使用限制存储器单元的漏极电压的变化的限压器来实现。

公开(公告)号：US08789165B2

公开(公告)日：2014-07-22

申请号：US13027834

申请日：2011-02-15

Applicant: Marco Bildgen ,  Jean Devin

Inventor： Marco Bildgen ,  Jean Devin

IPC: G06F21/00 ,  H04L29/06 ,  H04N7/167 ,  H04N7/20 ,  G06F15/16 ,  H04B1/16 ,  H04M11/00

CPC classification number: H04N7/1675 ,  G06F21/10 ,  G06F21/552 ,  G06F21/77 ,  G06F2221/0797 ,  G06F2221/2105 ,  G06F2221/2151 ,  G06F2221/2153 ,  H04L9/004 ,  H04L9/0637 ,  H04L63/1441 ,  H04N21/4181 ,  H04N21/4424 ,  H04N21/4432 ,  H04N21/4623

Abstract: A method may be for detecting potentially suspicious operation of an electronic device configured to operate in the course of activity sessions. The method may include within the device, a metering, from an initial instant of the number of activity sessions having a duration below a first threshold, and a comparison of this number with a second threshold.

Abstract translation: 一种方法可以用于检测被配置为在活动会话过程中操作的电子设备的潜在的可疑操作。 所述方法可以在所述设备内包括从具有低于第一阈值的持续时间的活动会话的数量的初始时刻的计量，以及所述数量与第二阈值的比较。

公开(公告)号：US07068538B2

公开(公告)日：2006-06-27

申请号：US10921365

申请日：2004-08-18

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C16/04

CPC classification number: G11C16/22

Abstract: A memory circuit comprising a memory area for storing data, a non-volatile memory area for storing at least one identification code, and a pin for storing the identification code in the non-volatile memory area. The memory circuit further comprising a programmable register in which a programmable state is fixed, wherein the programmable state indicates if the identification code has been stored in the non-volatile memory area, and a logic module which blocks any subsequent changes to the identification code fixed in the non-volatile memory area in response to the programmable state in the programmable register indicating that the identification code has been stored in the non-volatile area. The invention also relates to an associated method. The invention is useful particularly to avoid fraudulent reprogramming of the area containing the identification code. The invention also relates to an associated method.

Abstract translation: 一种存储电路，包括用于存储数据的存储区域，用于存储至少一个识别码的非易失性存储区域和用于将所述识别码存储在所述非易失性存储区域中的引脚。 存储器电路还包括其中可编程状态是固定的可编程寄存器，其中所述可编程状态指示所述识别码是否已被存储在所述非易失性存储器区域中;以及逻辑模块，其阻止所述识别码的任何后续改变被固定 响应于所述可编程寄存器中的所述可编程状态指示所述识别码已被存储在所述非易失性区域中，在所述非易失性存储器区域中。 本发明还涉及一种相关联的方法。 本发明特别适用于避免包含识别码的区域的欺骗性重新编程。 本发明还涉及一种相关联的方法。

公开(公告)号：US06621720B1

公开(公告)日：2003-09-16

申请号：US10019771

申请日：2001-12-27

Applicant: Jean Devin ,  Mohamad Chehadi

Inventor： Jean Devin ,  Mohamad Chehadi

IPC: H02M318

CPC classification number: G11C16/12 ,  G11C16/30

Abstract: The integrated circuit includes a detection circuit and a rectifier circuit that are series-connected, to provide a rectified voltage, and a low voltage regulation circuit that receives the rectified voltage and provides a low voltage. According to the invention, the circuit also has a voltage production circuit that receives the rectified voltage and produces a high voltage different from the low voltage. In one embodiment, the circuit also includes a memory having a memory array receiving the low voltage and the high voltage.

Abstract translation: 集成电路包括串联连接的提供整流电压的检测电路和整流电路，以及接收整流电压并提供低电压的低压调节电路。 根据本发明，电路还具有接收整流电压并产生不同于低电压的高电压的电压产生电路。 在一个实施例中，电路还包括具有接收低电压和高电压的存储器阵列的存储器。

公开(公告)号：US06420919B2

公开(公告)日：2002-07-16

申请号：US09742890

申请日：2000-12-21

Applicant: Bertrand Bertrand ,  Jean Devin

Inventor： Bertrand Bertrand ,  Jean Devin

IPC: H03K512

CPC classification number: H03K17/163

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract translation: 集成电路被电压提供电压，并且包括具有由逻辑电路的输出驱动的栅极的输出MOS晶体管和用于偏置输出MOS晶体管的栅极的电路。 用于偏置栅极的电路被提供用于相对于否则将由逻辑电路的输出提供的栅极 - 源偏置电压降低导通状态下的输出MOS晶体管的栅极 - 源极偏置电压。 本发明特别适用于I2C总线的输出级。