公开(公告)号：US20060011816A1

公开(公告)日：2006-01-19

申请号：US10536302

申请日：2003-11-13

申请人： Joachim Garbe ,  Wolfgang Buhr

发明人： Joachim Garbe ,  Wolfgang Buhr

IPC分类号： G11C16/22

CPC分类号： G06F21/75 ,  G11C16/22

摘要： In order to further develop a circuit arrangement (100) for electronic data communication, comprising—at least a non-volatile memory module (10) for storing data, and—at least an interface logic (20) associated with the memory module (10)—for addressing the memory module (10) and—for writing data to the memory module (10) or—for reading data from the memory module (10), together with a related method for registering light attacks on the non-volatile memory module (10), in such a way that, firstly, the light attack is recognized immediately and reliably regardless of whether an access, in particular a read access, to the memory module (10) is taking place or not and, secondly, the entire address space of the memory module (10) is covered as uniformly as possible in this regard, it is proposed that at least a monitoring arrangement (22) provided for monitoring the memory module (10) is associated with the interface logic (20), by means of which monitoring arrangement (22) an irradiation of the memory module (10) with at least a light source [so-called “light attack”] can be detected and/or registered and/or signaled in a test mode (T) in which no write or read access to the memory module (10) takes place.

摘要翻译： 为了进一步开发用于电子数据通信的电路装置（100），包括用于存储数据的至少一个非易失性存储器模块（10）以及至少与存储器模块（10）相关联的接口逻辑（20） ） - 用于寻址存储器模块（10），并用于将数据写入存储器模块（10）或用于从存储器模块（10）读取数据，以及用于将光攻击注册到非易失性存储器上的相关方法 模块（10），其特征在于，首先，无论是否对存储器模块（10）进行访问，特别是读取访问，都立即且可靠地识别光攻击，其次， 在这方面，存储模块（10）的整个地址空间被尽可能均匀地被覆盖，所以建议至少提供用于监视存储器模块（10）的监视装置（22）与接口逻辑（20）相关联， ，通过其进行监控 （22）可以以至少一个光源（即所谓的“光攻击”）照射存储器模块（所谓的“光攻击”），并且可以在没有写入的测试模式（T）中检测和/或注册和/或发信号通知 或者对存储器模块（10）进行读取访问。

公开(公告)号：US07473958B2

公开(公告)日：2009-01-06

申请号：US10535368

申请日：2003-11-13

申请人： Mathias Wagner ,  Joachim Garbe

发明人： Mathias Wagner ,  Joachim Garbe

IPC分类号： H01L27/115

CPC分类号： G11C16/22 ,  G06K19/07372 ,  H01L23/57 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to further develop an electronic memory component (100 or 100′), comprising at least one memory cell matrix (10) which is embedded in and/or let into at least one doped receiving substrate (20), in such a way that a light incidence taking the form of a so-called light attack is detected directly or sensed immediately without dead times (=contribution to chip development), it is proposed,—that the receiving substrate (20) be covered and/or surrounded at least partially and/or on at least one of its surfaces remote from the memory cell matrix (10) by at least one top/protective substrate (30) oppositely doped to the receiving substrate (20) and—that at least one of the substrates (20 or 30), for example the receiving substrate (20) and/or in particular the top/protective substrate (30), be in contact (12a or 12b) or connection (32) with at least one circuit arrangement (24 or 34 respectively) for the detection of voltages or currents caused by charge carriers generated upon light incidence.

摘要翻译： 为了进一步开发电子存储器组件（100或100'），包括至少一个存储单元矩阵（10），其被嵌入和/或放入至少一个掺杂的接收衬底（20）中，使得 直接检测出所谓光攻击形式的光入射，或立即检测到没有死时间（=对芯片开发的贡献）， - 接收基板（20）至少被覆盖和/或包围 部分地和/或在其远离存储单元矩阵（10）的至少一个表面上的相对地掺杂到接收衬底（20）的至少一个顶部/保护衬底（30）和至少一个衬底（ 20或30），例如接收衬底（20）和/或特别是顶部/保护衬底（30）与至少一个电路装置（24或34）接触（12a或12b）或连接（32） 分别）用于检测由在ligh上产生的电荷载流子引起的电压或电流 t发病率。

公开(公告)号：US20060081912A1

公开(公告)日：2006-04-20

申请号：US10535368

申请日：2003-11-13

申请人： Mathias Wagner ,  Joachim Garbe

发明人： Mathias Wagner ,  Joachim Garbe

IPC分类号： H01L29/788

CPC分类号： G11C16/22 ,  G06K19/07372 ,  H01L23/57 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to further develop an electronic memory component (100 or 100′), comprising at least one memory cell matrix (10) which is embedded in and/or let into at least one doped receiving substrate (20), in such a way that a light incidence taking the form of a so-called light attack is detected directly or sensed immediately without dead times (=contribution to chip development), it is proposed,—that the receiving substrate (20) be covered and/or surrounded at least partially and/or on at least one of its surfaces remote from the memory cell matrix (10) by at least one top/protective substrate (30) oppositely doped to the receiving substrate (20) and—that at least one of the substrates (20 or 30), for example the receiving substrate (20) and/or in particular the top/protective substrate (30), be in contact (12a or 12b) or connection (32) with at least one circuit arrangement (24 or 34 respectively) for the detection of voltages or currents caused by charge carriers generated upon light incidence.

摘要翻译： 为了进一步开发电子存储器组件（100或100'），包括至少一个存储单元矩阵（10），其被嵌入和/或放入至少一个掺杂的接收衬底（20）中，使得 直接检测出所谓光攻击形式的光入射，或立即检测到没有死时间（=对芯片开发的贡献）， - 接收基板（20）至少被覆盖和/或包围 部分地和/或在其远离存储单元矩阵（10）的至少一个表面上的相对地掺杂到接收衬底（20）的至少一个顶部/保护衬底（30）和至少一个衬底（ 20或30），例如接收衬底（20）和/或特别是顶部/保护衬底（30）与至少一个电路装置（24）接触（12a或12b）或连接（32） 或34）用于检测由电荷引起的电压或电流 光照发生时产生的光环。

公开(公告)号：US20100299756A1

公开(公告)日：2010-11-25

申请号：US12299950

申请日：2007-05-03

申请人： Soenke Ostertun ,  Joachim Garbe ,  Johannes Toriyabe

发明人： Soenke Ostertun ,  Joachim Garbe ,  Johannes Toriyabe

IPC分类号： G06F21/00

CPC分类号： G06K19/07363 ,  G06K19/07345

摘要： The invention relates to a sensor, in particular for detecting attacks on at least one signal-carrying line (11), in particular of chip cards (1), said sensor having a circuit arrangement (10) which comprises a first circuit arrangement (13) for detecting an instantaneous voltage value above a first supply voltage and a second circuit arrangement (14) for detecting an instantaneous voltage value below a second supply voltage, wherein, when a voltage value outside the range between the first and second supply voltages is detected, a signal (19) is generated and can be taken as a basis for initiating a protective measure.

摘要翻译： 本发明涉及一种传感器，特别是用于检测至少一条信号传输线路（11），特别是芯片卡（1）的攻击，所述传感器具有电路装置（10），该电路装置包括第一电路装置 ），用于检测高于第一电源电压的瞬时电压值;以及第二电路装置（14），用于检测低于第二电源电压的瞬时电压值，其中当检测到在第一和第二电源电压之间的范围之外的电压值时 ，产生信号（19），并且可以作为启动保护措施的基础。

公开(公告)号：US20050052918A1

公开(公告)日：2005-03-10

申请号：US10497262

申请日：2002-10-24

申请人： Guido Dormans ,  Robertus Verhaar ,  Joachim Garbe

发明人： Guido Dormans ,  Robertus Verhaar ,  Joachim Garbe

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H04L12/00 ,  G11C7/00

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/16

摘要： The invention relates to a semiconductor device having a byte-erasable EEPROM memory comprising a matrix of rows and columns of memory cells. In order to provide a semiconductor device having a byte-erasable EEPROM which has a reduced chip size and increased density and which is suitable for low-power applications it is proposed according to the present invention that the memory cells each comprise a selection transistor having a selection gate and, arranged in series therewith, a memory transistor having a floating gate and a control gate, the selection transistor being further connected to a source line of the byte-erasable EEPROM memory, which source line is common for a plurality of memory cells, and the memory transistor being further connected to a bit line of the byte-erasable EEPROM memory, wherein the columns of memory cells are located in separate p-type wells separated by n-type wells. Preferably, high voltage switching elements are provided for dividing global control gates into local control gates for each column of bytes.

摘要翻译： 本发明涉及一种具有字节可擦除EEPROM存储器的半导体器件，其包括存储器单元的行和列的矩阵。 为了提供具有字节可擦除EEPROM的半导体器件，其具有减小的芯片尺寸和增加的密度，并且适用于低功率应用，根据本发明提出，存储器单元各自包括选择晶体管，其具有 选择栅极，与串联布置的具有浮置栅极和控制栅极的存储晶体管，所述选择晶体管进一步连接到所述字节可擦除EEPROM存储器的源极线，所述源极线对于多个存储单元是公共的 并且存储晶体管进一步连接到字节可擦除EEPROM存储器的位线，其中存储器单元的列位于由n型阱分离的单独的p型阱中。 优选地，提供高压开关元件，用于将全局控制门分成用于每列字节的本地控制门。