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公开(公告)号:US12034876B2
公开(公告)日:2024-07-09
申请号:US17620401
申请日:2020-06-18
申请人: TTP Plc.
发明人: Timothy John Palmer , Michael Beck
CPC分类号: H04L9/3278 , H01L23/57 , H04L2209/12
摘要: A physically unclonable function (PUF) device comprises a plurality of conductors, at least some of which are arranged so that they interact electrically and/or magnetically with one another. A media surrounds at least a portion of each of the conductors and a plurality of temperature compensation particles are arranged throughout the media, where the temperature compensation particles have a temperature coefficient selected such that they compensate for temperature-related effects in the PUF device by making the permittivity and/or permeability of the media substantially temperature independent. Circuitry applies an electrical challenge signal to at least one or the conductors and receives an electrical output from at least one of the other conductors to generate an identifying response to the challenge signal that is unique to the device.
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公开(公告)号:US11889004B2
公开(公告)日:2024-01-30
申请号:US17816315
申请日:2022-07-29
发明人: Martin Koenig
CPC分类号: H04L9/3278 , G06F21/72 , G06F21/75 , G06F21/86 , H01L21/00 , H01L23/57 , H01L23/573 , H01L28/60 , H04L9/0861 , H04L9/0866 , H04L2209/12
摘要: A method for producing a PUF-film includes printing a layer of dielectric material on a film substrate, such that a variable thickness of the layer is obtained by the printing. The method includes arranging a structured electrode layer on the dielectric material such that the structured electrode layer is influenced with respect to an electric measurement value due to the variable thickness.
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公开(公告)号:US20240006345A1
公开(公告)日:2024-01-04
申请号:US17874299
申请日:2022-07-27
发明人: Po Hsien Chen , Ping-Chia Shih , Che Hao Kuo , Chia-Min Hung , Ching-Hua Yeh , Wan-Chun Liao
CPC分类号: H01L23/57 , H04L9/3278 , H01L29/0649
摘要: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.
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公开(公告)号:US20190244915A1
公开(公告)日:2019-08-08
申请号:US16267573
申请日:2019-02-05
CPC分类号: H01L23/57 , G06F21/75 , G06F21/77 , G06K19/07372 , H01L23/576
摘要: A semiconductor substrate of an integrated circuit is protected by a coating. The semiconductor includes a front face and a rear face. To detect a breach of the integrity of a semiconductor substrate of an integrated circuit from the rear face, an opening of the coating facing the rear face of the substrate is detected. In response thereto, an alarm is generated. The detection is performed by making resistance measurements with respect to the semiconductor substrate and comparing the measured resistance to a nominal resistive value of the semiconductor substrate.
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公开(公告)号:US20180302095A1
公开(公告)日:2018-10-18
申请号:US16011977
申请日:2018-06-19
IPC分类号: H03K19/177 , G06F17/50 , H03K17/30 , G06F21/75 , H01L23/00
CPC分类号: H03K19/17768 , G06F11/0706 , G06F11/0751 , G06F11/079 , G06F11/0793 , G06F17/50 , G06F21/75 , H01L23/57 , H01L29/80 , H03K17/302
摘要: Disclosed are various embodiments providing circuitry that includes camouflaged gates that each have multiple switches arranged in a predefined format. A switch at a specific position in one camouflaged gate can have a different threshold voltage than a switch at the specific position in another camouflaged gate. The logical function performed by the camouflaged gate can be based on which of the switches have a low threshold voltage and which of the switches have a high threshold voltage.
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公开(公告)号:US20180277198A1
公开(公告)日:2018-09-27
申请号:US15464377
申请日:2017-03-21
发明人: Po-Hao Tseng , Kai-Chieh Hsu
IPC分类号: G11C11/419 , H01L23/00 , H01L27/11 , H01L23/535
CPC分类号: H01L23/535 , G11C7/1006 , G11C7/24 , G11C17/16 , H01L23/57 , H01L27/11226
摘要: A semiconductor device includes a programmable memory array comprising plural memory units disposed above a substrate. One of the memory units comprises a gate electrode disposed above the substrate, a conductive portion spaced apart from the gate electrode, and a dielectric layer contacting the conductive portion and separated from the gate electrode, and the dielectric layer defining a threshold voltage of the related memory unit, wherein at least two of the memory units have different threshold voltages.
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公开(公告)号:US09997466B2
公开(公告)日:2018-06-12
申请号:US15352405
申请日:2016-11-15
发明人: Eric E. Vogt , Gregor D. Dougal , James L. Tucker
IPC分类号: H01L23/538 , H01L21/48
CPC分类号: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L23/13 , H01L23/28 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L23/57 , H01L23/573 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/48145 , H01L2224/73253 , H01L2224/73257 , H01L2224/81193 , H01L2224/81203 , H01L2224/81895 , H01L2224/81896 , H01L2224/83805 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2924/10253 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1436 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00012
摘要: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
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公开(公告)号:US20180018125A1
公开(公告)日:2018-01-18
申请号:US15210567
申请日:2016-07-14
IPC分类号: G06F3/06
CPC分类号: G06F3/0652 , G06F3/0623 , G06F3/064 , G06F3/0679 , G06F21/86 , H01L23/57 , Y04S40/24
摘要: An apparatus embodiment includes an integrated circuit (IC) and breach-detection circuitry. The IC includes data storage circuitry, a power grid configured to distribute power to the data storage circuitry, and a plurality of nodes distributed over at least one sensitive region of the IC. The breach-detection circuitry monitors power grid integrity at the at least one sensitive region of the IC and detects an event indicative of a breach by an external probe at a portion of the at least one sensitive region in response to floating node detection or a change in voltage at one of the plurality of nodes.
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公开(公告)号:US20180005963A1
公开(公告)日:2018-01-04
申请号:US15689566
申请日:2017-08-29
IPC分类号: H01L23/00 , H01L23/15 , H01L25/065 , H01L23/498 , H03K19/177 , H01L21/48
CPC分类号: H01L23/573 , H01L21/4853 , H01L21/486 , H01L21/4864 , H01L23/15 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/57 , H01L23/576 , H01L24/00 , H01L24/16 , H01L25/0655 , H01L2224/16157 , H01L2224/16235 , H01L2924/15311 , H03K19/17768
摘要: A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).
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公开(公告)号:US09853001B1
公开(公告)日:2017-12-26
申请号:US15195149
申请日:2016-06-28
发明人: Qing Cao , Kangguo Cheng , Zhengwen Li , Fei Liu
CPC分类号: H01L23/57 , H01L21/56 , H01L23/3142 , H01L23/3157 , H01L23/573 , H01L2924/3512
摘要: A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric reactant; and a sealant layer arranged on a surface of the self-destructive layer, on sidewalls of the self-destructive layer, and on the chip substrate such that the sealant layer forms a package seal on the semiconductor chip; wherein the pyrophoric reactant ignites spontaneously upon exposure to air.
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