公开(公告)号：US20120038616A1

公开(公告)日：2012-02-16

申请号：US13104087

申请日：2011-05-10

Applicant: JunYong SONG ,  Jaehoon LEE ,  Yu-Han BAE

Inventor： JunYong SONG ,  Jaehoon LEE ,  Yu-Han BAE

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G3/003 ,  G09G2310/08

Abstract: A display apparatus includes: a display panel which displays an image based on a display mode; a data driver which provides data signals to the display panel; a gate driver which starts an operation thereof in response to a start signal, and comprises stages and at least two dummy stages, where the stages sequentially provides gate signals to the display panel; and a timing controller which selects a signal from the start signal and a reset signal based on the display mode and outputs the selected signal selected to the at least two dummy stages, where each stage receives a clock signal, a previous carry signal from a previous stage, a first subsequent carry signal from a first subsequent stage and a second subsequent carry signal from a second subsequent stage, and outputs a corresponding gate signal of the gate signals and a carry signal.

Abstract translation: 显示装置包括：基于显示模式显示图像的显示面板; 数据驱动器，其向显示面板提供数据信号; 门驱动器，其响应于起始信号开始其操作，并且包括级和至少两个虚级，其中级顺序地向显示面板提供门信号; 以及定时控制器，其基于所述显示模式选择来自所述起始信号的信号和复位信号，并且将选择的所选择的信号输出到所述至少两个虚拟级，其中每个级接收时钟信号，来自前一个的先前进位信号 来自第一后续级的第一后续进位信号和来自第二后续级的第二后续进位信号，并输出门信号和进位信号的对应门信号。

公开(公告)号：US20130256774A1

公开(公告)日：2013-10-03

申请号：US13742940

申请日：2013-01-16

Applicant: Namho JEON ,  Jun-Su KIM ,  Satoru YAMADA ,  Jaehoon LEE ,  Seunguk HAN ,  Jiyoung KIM ,  Jin-Seong LEE

Inventor： Namho JEON ,  Jun-Su KIM ,  Satoru YAMADA ,  Jaehoon LEE ,  Seunguk HAN ,  Jiyoung KIM ,  Jin-Seong LEE

IPC: H01L29/78

CPC classification number: H01L29/7831 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L27/105 ,  H01L27/115

Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.

Abstract translation: 半导体存储器件可以包括写入晶体管，其包括控制第一源极/漏极端子的第一写入栅极和控制沟道区域的第二写入栅极，以及读取晶体管，其包括连接到写入的第一源极/漏极端子的存储器节点栅极 晶体管。 第一写入门可以具有第一工作功能，并且第二写入门可以具有与第一工作功能不同的第二工作功能。 写晶体管的第一源极/漏极端子可以不具有PN结。

公开(公告)号：US20130093739A1

公开(公告)日：2013-04-18

申请号：US13419726

申请日：2012-03-14

Applicant: Ji-Sun KIM ,  Yeong-Keun KWON ,  Soo-Wan YOON ,  Young-Soo YOON ,  Jaehoon LEE ,  Chongchul CHAI

Inventor： Ji-Sun KIM ,  Yeong-Keun KWON ,  Soo-Wan YOON ,  Young-Soo YOON ,  Jaehoon LEE ,  Chongchul CHAI

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0434

Abstract: A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows.

Abstract translation: 显示装置包括栅极线，与栅极线绝缘的数据线，同时跨越栅极线，以及每个包括具有三个连续列的两个连续行中的子像素的像素。 在三列中的两行中的子像素之中，三列之一中的一个子像素分别连接到三条栅极线中的一对不同的栅极线，并且不同的一个像素 三列连接到三条栅极线之间的剩余栅极线。 三列中的一个子像素和不同的一个子像素包括相同的滤色器，并施加沿像素行沿相同方向传输的栅极信号。