公开(公告)号：US20120038616A1

公开(公告)日：2012-02-16

申请号：US13104087

申请日：2011-05-10

Applicant: JunYong SONG ,  Jaehoon LEE ,  Yu-Han BAE

Inventor： JunYong SONG ,  Jaehoon LEE ,  Yu-Han BAE

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G3/003 ,  G09G2310/08

Abstract: A display apparatus includes: a display panel which displays an image based on a display mode; a data driver which provides data signals to the display panel; a gate driver which starts an operation thereof in response to a start signal, and comprises stages and at least two dummy stages, where the stages sequentially provides gate signals to the display panel; and a timing controller which selects a signal from the start signal and a reset signal based on the display mode and outputs the selected signal selected to the at least two dummy stages, where each stage receives a clock signal, a previous carry signal from a previous stage, a first subsequent carry signal from a first subsequent stage and a second subsequent carry signal from a second subsequent stage, and outputs a corresponding gate signal of the gate signals and a carry signal.

Abstract translation: 显示装置包括：基于显示模式显示图像的显示面板; 数据驱动器，其向显示面板提供数据信号; 门驱动器，其响应于起始信号开始其操作，并且包括级和至少两个虚级，其中级顺序地向显示面板提供门信号; 以及定时控制器，其基于所述显示模式选择来自所述起始信号的信号和复位信号，并且将选择的所选择的信号输出到所述至少两个虚拟级，其中每个级接收时钟信号，来自前一个的先前进位信号 来自第一后续级的第一后续进位信号和来自第二后续级的第二后续进位信号，并输出门信号和进位信号的对应门信号。

公开(公告)号：US20120162187A1

公开(公告)日：2012-06-28

申请号：US13274939

申请日：2011-10-17

Applicant: Jae-Hoon LEE ,  Chang-Ho LEE ,  Jun-Yong SONG ,  Yu-Han BAE

Inventor： Jae-Hoon LEE ,  Chang-Ho LEE ,  Jun-Yong SONG ,  Yu-Han BAE

IPC: G09G5/00 ,  H03B1/00

CPC classification number: G09G3/007 ,  G09G3/29 ,  G09G2300/0838 ,  G09G2300/0871 ,  G09G2310/0286 ,  G09G2310/0289

Abstract: A gate drive circuit includes a plurality of driving stages. An n-th (‘n’ is a natural number) driving stage includes a pull-up part, a carry part, a first pull-down part, a first pull-up/down control part and a second pull-up/down control part. The first pull-up/down control part applies a first power signal of an ON voltage to a control terminal of the pull-up part in a forward direction mode, and applies the first power signal of a second OFF voltage to a control terminal of the pull-up part in a reverse direction mode. The second pull-up/down control part applies a second power signal of the second OFF voltage to the control terminal of the pull-up part in the forward direction mode, and applies the second power signal of the ON voltage to the control terminal of the pull-up part in the reverse direction mode.

Abstract translation: 栅极驱动电路包括多个驱动级。 第n（'n'是自然数）驱动级包括上拉部分，进位部分，第一下拉部分，第一上拉/下拉控制部分和第二上拉/下拉 控制部分。 第一上拉/下拉控制部分向前向模式向上拉部分的控制端施加导通电压的第一电源信号，并将第二OFF电压的第一电源信号施加到 上拉部分处于反向模式。 第二上拉/下拉控制部分将第二OFF电压的第二功率信号以正向模式施加到上拉部分的控制端，并将接通电压的第二功率信号施加到 上拉部分处于反向模式。

公开(公告)号：US20120212401A1

公开(公告)日：2012-08-23

申请号：US13242379

申请日：2011-09-23

Applicant: Yu-Han BAE ,  Jae-Hoon LEE ,  Seung-Hwan MOON

Inventor： Yu-Han BAE ,  Jae-Hoon LEE ,  Seung-Hwan MOON

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2310/02 ,  G09G2310/0243 ,  G09G2310/0251 ,  G09G2310/0281 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2320/0223

Abstract: A display panel includes a display area, a peripheral area which includes a first peripheral area, and a second peripheral area opposite to the first peripheral area, a plurality of pixels in the display area, a plurality of data lines, a first gate line, a second gate line, a first gate driving circuit and a second gate driving circuit. Each data line corresponds to two pixel columns. The first gate line is at a first side of a pixel row. The second gate line is at a second side of the pixel row. The first gate driving circuit is in the first peripheral area and includes a first stage which provides a gate signal to the first gate line. The second gate driving circuit is in a second peripheral area of the display area and includes a second stage which provides a gate signal to the second gate line.

Abstract translation: 显示面板包括显示区域，包括第一外围区域的外围区域和与第一外围区域相反的第二外围区域，显示区域中的多个像素，多个数据线，第一栅极线， 第二栅极线，第一栅极驱动电路和第二栅极驱动电路。 每个数据线对应于两个像素列。 第一个栅极线位于像素行的第一侧。 第二栅极线位于像素行的第二侧。 第一栅极驱动电路在第一周边区域中，并且包括向第一栅极线提供栅极信号的第一级。 第二栅极驱动电路在显示区域的第二周边区域中，并且包括向第二栅极线提供栅极信号的第二级。

公开(公告)号：US20100141672A1

公开(公告)日：2010-06-10

申请号：US12473815

申请日：2009-05-28

Applicant: Hyung-Ku KANG ,  Hyuk-Hwan KIM ,  Dae-Gwang JANG ,  Yu-Han BAE ,  Hyeon-Yong JANG

Inventor： Hyung-Ku KANG ,  Hyuk-Hwan KIM ,  Dae-Gwang JANG ,  Yu-Han BAE ,  Hyeon-Yong JANG

IPC: G09G3/36 ,  H05B39/04 ,  G09G5/02

CPC classification number: H05B37/02 ,  G09G3/342 ,  G09G3/3426 ,  G09G3/3648 ,  G09G5/10 ,  G09G2320/0233 ,  G09G2320/041 ,  G09G2320/064 ,  G09G2320/0646 ,  G09G2320/066 ,  G09G2330/028 ,  G09G2360/16 ,  H05B33/0866

Abstract: A light source device includes a light source module having a light-emitting block, an image analysis part, a duty ratio calculation part, a duty ratio determination part and a signal generation part. The image analysis part extracts representative luminance data of the light-emitting block based on pixel data. The duty ratio calculation part calculates duty ratio data of the light-emitting block based on the representative luminance data. The duty ratio determination part generates determined duty ratio data of the light-emitting block based on the duty ratio data from a first period, and the signal generation part generates a driving signal having a duty ratio corresponding to the determined duty ratio data to drive the light-emitting block.

Abstract translation: 光源装置包括具有发光块，图像分析部，占空比计算部，占空比确定部和信号生成部的光源模块。 图像分析部基于像素数据提取发光块的代表亮度数据。 占空比计算部根据代表亮度数据计算发光块的占空比数据。 占空比确定部分基于来自第一周期的占空比数据产生确定的发光块的占空比数据，并且信号产生部分产生具有与确定的占空比数据相对应的占空比的驱动信号，以驱动 发光块。

公开(公告)号：US20120162184A1

公开(公告)日：2012-06-28

申请号：US13209521

申请日：2011-08-15

Applicant: Young-Su KIM ,  Jae-Hoon LEE ,  Chang-Ho LEE ,  Yu-Han BAE

Inventor： Young-Su KIM ,  Jae-Hoon LEE ,  Chang-Ho LEE ,  Yu-Han BAE

IPC: G09G5/00

CPC classification number: G09G3/3655 ,  G09G2320/0214

Abstract: A method of driving a display panel includes applying a common voltage to the display panel, sensing a frequency of the display panel to generate a frequency signal, adjusting a gain of an operational amplifier based on the frequency signal, receiving a feedback common voltage from the display panel, and compensating the common voltage using an input resistor, the operational amplifier and a feedback resistor based on the feedback common voltage to apply the compensated common voltage to the display panel. The operational amplifier includes an inverting input terminal connected to the input resistor, a non-inverting input terminal to which a reference common voltage is applied and an output terminal. The feedback resistor is between the inverting input terminal and the output terminal.

Abstract translation: 驱动显示面板的方法包括向显示面板施加公共电压，感测显示面板的频率以产生频率信号，基于频率信号调整运算放大器的增益，从所述频率信号接收反馈公共电压 显示面板，并使用输入电阻器，运算放大器和基于反馈公共电压的反馈电阻器补偿公共电压，以将补偿的公共电压施加到显示面板。 运算放大器包括连接到输入电阻器的反相输入端子，施加参考公共电压的非反相输入端子和输出端子。 反馈电阻位于反相输入端和输出端之间。

公开(公告)号：US20120139883A1

公开(公告)日：2012-06-07

申请号：US13292661

申请日：2011-11-09

Applicant: Jae-Hoon LEE ,  Young-Su KIM ,  Whee-Won LEE ,  Jun-Yong SONG ,  Yu-Han BAE ,  You-Mee HYUN

Inventor： Jae-Hoon LEE ,  Young-Su KIM ,  Whee-Won LEE ,  Jun-Yong SONG ,  Yu-Han BAE ,  You-Mee HYUN

IPC: G06F3/038 ,  H03K3/00

CPC classification number: G09G3/3611 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/041 ,  G11C19/28

Abstract: A gate drive circuit includes a shift register in which plural stages are cascade-connected to each other. In an n-th stage, a pull-up part outputs a high voltage of a clock signal to an output node as a high voltage of an n-th gate signal in response to a high voltage on a first node. A pull-down part pulls the high voltage of the n-th gate signal down to a first low voltage in response to an (n+1)th carry signal. A discharging part discharges the first node to a second low voltage level lower than the first low voltage level in response to the (n+1)th carry signal. A carry part outputs the high voltage of the clock signal as an n-th carry signal (mirroring the n-th gate signal) in response to a high voltage on the first node.

Abstract translation: 栅极驱动电路包括其中多级级联连接的移位寄存器。 在第n级中，上拉部分响应于第一节点上的高电压，将时钟信号的高电压输出到输出节点作为第n栅极信号的高电压。 下拉部分响应于第（n + 1）个进位信号将第n个门信号的高电压降低到第一低电压。 放电部分响应于第（n + 1）个进位信号，将第一节点放电到比第一低电压电平低的第二低电压电平。 进位部分响应于第一节点上的高电压，输出时钟信号的高电压作为第n个进位信号（反映第n个门信号）。

公开(公告)号：US20100265238A1

公开(公告)日：2010-10-21

申请号：US12762470

申请日：2010-04-19

Applicant: Jae-Hoon LEE ,  Yong-Soon LEE ,  Young-Su KIM ,  Yu-Han BAE

Inventor： Jae-Hoon LEE ,  Yong-Soon LEE ,  Young-Su KIM ,  Yu-Han BAE

IPC: G06F3/038 ,  H01J9/00

CPC classification number: G09G3/3614 ,  G09G3/3607 ,  G09G2300/0426 ,  G09G2320/0209

Abstract: A display device includes a display panel, a data driving part and a gate driving part. The display panel includes a first pixel row. The first pixel row includes a first pixel connected to an (n+1)-th gate line and an (m+1)-th data line (where ‘n’ and ‘m’ are natural numbers), and a second pixel connected to an n-th gate line and an (m+2)-th data line. The data driving part applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line, and applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th data line. The gate driving part sequentially applies a gate signal to the n-th gate line and the (n+1)-th gate line.

Abstract translation: 显示装置包括显示面板，数据驱动部和门驱动部。 显示面板包括第一像素行。 第一像素行包括连接到第（n + 1）栅极线和第（m + 1）数据线（其中'n'和'm'是自然数）的第一像素，并且第二像素连接 到第n个栅极线和第（m + 2）个数据线。 数据驱动部分对第（m + 1）数据线施加相对于参考电压具有第一极性的数据电压，并将相对于参考电压具有第二极性的数据电压施加到第（m + 2）数据线。 栅极驱动部分顺序地对第n条栅极线和第（n + 1）栅极线施加栅极信号。