公开(公告)号：US20120038616A1

公开(公告)日：2012-02-16

申请号：US13104087

申请日：2011-05-10

Applicant: JunYong SONG ,  Jaehoon LEE ,  Yu-Han BAE

Inventor： JunYong SONG ,  Jaehoon LEE ,  Yu-Han BAE

IPC: G09G5/00

CPC classification number: G09G3/3677 ,  G09G3/003 ,  G09G2310/08

Abstract: A display apparatus includes: a display panel which displays an image based on a display mode; a data driver which provides data signals to the display panel; a gate driver which starts an operation thereof in response to a start signal, and comprises stages and at least two dummy stages, where the stages sequentially provides gate signals to the display panel; and a timing controller which selects a signal from the start signal and a reset signal based on the display mode and outputs the selected signal selected to the at least two dummy stages, where each stage receives a clock signal, a previous carry signal from a previous stage, a first subsequent carry signal from a first subsequent stage and a second subsequent carry signal from a second subsequent stage, and outputs a corresponding gate signal of the gate signals and a carry signal.

Abstract translation: 显示装置包括：基于显示模式显示图像的显示面板; 数据驱动器，其向显示面板提供数据信号; 门驱动器，其响应于起始信号开始其操作，并且包括级和至少两个虚级，其中级顺序地向显示面板提供门信号; 以及定时控制器，其基于所述显示模式选择来自所述起始信号的信号和复位信号，并且将选择的所选择的信号输出到所述至少两个虚拟级，其中每个级接收时钟信号，来自前一个的先前进位信号 来自第一后续级的第一后续进位信号和来自第二后续级的第二后续进位信号，并输出门信号和进位信号的对应门信号。

公开(公告)号：US20160163704A1

公开(公告)日：2016-06-09

申请号：US14958078

申请日：2015-12-03

Applicant: JAEHOON LEE

Inventor： JAEHOON LEE

IPC: H01L27/092 ,  H01L29/778 ,  H01L29/10

CPC classification number: H01L27/0922 ,  H01L21/8258 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first source are disposed on the first buffer layer and have heterogeneous structures. A first channel is disposed between the first drain and the first source. A first gate electrode is disposed on the first channel. A second drain and a second source are disposed on the first buffer layer. A second channel is disposed between the second drain and the second source. The second channel includes a different material from the first channel. A second gate electrode is disposed on the second channel. The first drain, the first source, the first channel and the first gate electrode are disposed in the NMOS region. The second drain, the second source, the second channel and the second gate electrode are disposed in the PMOS region.

Abstract translation: 如下提供半导体器件。 第一缓冲层设置在包括NMOS和PMOS区的衬底上。 第一漏极和第一源极设置在第一缓冲层上并且具有异质结构。 第一通道设置在第一漏极和第一源极之间。 第一栅电极设置在第一通道上。 第二漏极和第二源极设置在第一缓冲层上。 第二通道设置在第二漏极和第二源极之间。 第二通道包括与第一通道不同的材料。 第二栅电极设置在第二通道上。 第一漏极，第一源极，第一沟道和第一栅电极设置在NMOS区域中。 第二漏极，第二源极，第二沟道和第二栅极设置在PMOS区域中。

公开(公告)号：US09293097B2

公开(公告)日：2016-03-22

申请号：US13419726

申请日：2012-03-14

Applicant: Ji-Sun Kim ,  Yeong-Keun Kwon ,  Soo-Wan Yoon ,  Young-Soo Yoon ,  Jaehoon Lee ,  Chongchul Chai

Inventor： Ji-Sun Kim ,  Yeong-Keun Kwon ,  Soo-Wan Yoon ,  Young-Soo Yoon ,  Jaehoon Lee ,  Chongchul Chai

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0434

Abstract: A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows.

Abstract translation: 显示装置包括栅极线，与栅极线绝缘的数据线，同时跨越栅极线，以及每个包括具有三个连续列的两个连续行中的子像素的像素。 在三列中的两行中的子像素之中，三列之一中的一个子像素分别连接到三条栅极线中的一对不同的栅极线，并且不同的一个像素 三列连接到三条栅极线之间的剩余栅极线。 三列中的一个子像素和不同的一个子像素包括相同的滤色器，并施加沿像素行沿相同方向传输的栅极信号。

公开(公告)号：US08730144B2

公开(公告)日：2014-05-20

申请号：US12982473

申请日：2010-12-30

Applicant: Chang Ho Lee ,  Jaehoon Lee

Inventor： Chang Ho Lee ,  Jaehoon Lee

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2320/041 ,  G11C19/28

Abstract: A driving circuit includes a plurality of stages driven in response to a start signal. Each normal stage outputs a gate signal and a carry signal, increases an electric potential of a node in response to a previous carry signal of a previous stage, and decreases the gate signal to a first voltage in response to a carry signal from a next stage. Each stage applies a second voltage lower than the first voltage to the node in response to receipt of a carry signal from a second next stage. A first dummy stage outputs a first dummy carry signal to the last two normal stages in response to a last carry signal from the last normal stage and the start signal, and a second dummy stage outputs a second dummy carry signal to the last normal stage in response to the first dummy carry signal and the start signal.

Abstract translation: 驱动电路包括响应于起始信号而驱动的多个级。 每个正常级输出门信号和进位信号，响应于先前级的先前进位信号增加节点的电位，并且响应于来自下一级的进位信号而将栅极信号减小到第一电压 。 响应于接收到来自第二下一级的进位信号，每个阶段将比第一电压低的第二电压施加到节点。 第一伪级响应于来自最后正常级的最后进位信号和起始信号而将第一伪进位信号输出到最后两个正常级，并且第二虚拟级将第二伪进位信号输出到最后正常级 对第一伪进位信号和起始信号的响应。

公开(公告)号：US20060045763A1

公开(公告)日：2006-03-02

申请号：US11212954

申请日：2005-08-26

Applicant: Jaehoon Lee ,  Jeonghun Seo ,  Haksoo Kim ,  Hewnam Ahn

Inventor： Jaehoon Lee ,  Jeonghun Seo ,  Haksoo Kim ,  Hewnam Ahn

IPC: F04B27/08 ,  F04B39/00

CPC classification number: F04B39/0061 ,  F04B27/1081

Abstract: The present invention relates to a compressor for sucking, compressing and discharging a refrigerant gas from the external refrigerant circuit. The compressor includes: a suction muffler chamber having a suction port formed on the outer circumference of a cylinder block, which has a plurality of bores arranged in a line, and an oil storing part for storing oil, the suction port being communicated with the external refrigerant circuit; and a rear housing connected to the cylinder block to close the rear end of the cylinder block and having a suction chamber and a discharge chamber therein, the rear housing having a suction chamber communicating passage for communicating the suction chamber with the suction muffler chamber at the upstream part of the suction chamber. The compressor can effectively reduce a pressure pulsation of the suction gas and a noise due to the pressure pulsation without causing an increase of the overall length and the entire volume of the compressor, improve lubrication at the time of an initial start, and increase suction and compression efficiencies.

Abstract translation: 本发明涉及一种用于从外部制冷剂回路吸入，压缩和排出制冷剂气体的压缩机。 压缩机包括：吸入消声器室，其具有形成在气缸体的外周上的吸入口，该吸入口具有排列成一行的多个孔和用于储存油的储油部，所述吸入口与外部连通 制冷剂回路; 以及后壳体，其连接到所述气缸体，以封闭所述气缸体的后端并且在其中具有吸入室和排出室，所述后壳体具有吸入室连通通道，用于将所述吸入室与所述吸入消声器室连通 吸入室的上游部分。 压缩机可以有效地减少吸入气体的压力脉动和由于压力脉动引起的噪音，而不会导致压缩机的总长度和整个体积的增加，从而改善初始启动时的润滑，并增加吸入和 压缩效率。

公开(公告)号：US20160163788A1

公开(公告)日：2016-06-09

申请号：US14958146

申请日：2015-12-03

Applicant: JAEHOON LEE

Inventor： JAEHOON LEE

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L27/092

CPC classification number: H01L29/0615 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/1054 ,  H01L29/16

Abstract: A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.

Abstract translation: 如下提供半导体器件。 衬底包括NMOS区和PMOS区。 第一沟槽和第二沟槽设置在NMOS区域中。 第一缓冲层设置在第一沟槽和第二沟槽中。 应力器设置在第一沟槽和第二沟槽中并且设置在第一缓冲层上。 第一沟道区域设置在第一沟槽和第二沟槽之间并且设置在衬底中。 第一栅电极设置在第一沟道区上。 第三沟槽设置在PMOS区域中。 第二缓冲层设置在第三沟槽中。 第二沟道区域设置在第三沟槽中，设置在第二缓冲层上，并且与衬底具有不同的半导体层。 第二栅电极设置在第二沟道区上。

公开(公告)号：US08809930B2

公开(公告)日：2014-08-19

申请号：US13742940

申请日：2013-01-16

Applicant: Namho Jeon ,  Jun-Su Kim ,  Satoru Yamada ,  Jaehoon Lee ,  Seunguk Han ,  Jiyoung Kim ,  Jin-Seong Lee

Inventor： Namho Jeon ,  Jun-Su Kim ,  Satoru Yamada ,  Jaehoon Lee ,  Seunguk Han ,  Jiyoung Kim ,  Jin-Seong Lee

IPC: H01L29/76

CPC classification number: H01L29/7831 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L27/105 ,  H01L27/115

Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.

Abstract translation: 半导体存储器件可以包括写入晶体管，其包括控制第一源极/漏极端子的第一写入栅极和控制沟道区域的第二写入栅极，以及读取晶体管，其包括连接到写入的第一源极/漏极端子的存储器节点栅极 晶体管。 第一写入门可以具有第一工作功能，并且第二写入门可以具有与第一工作功能不同的第二工作功能。 写晶体管的第一源极/漏极端子可以不具有PN结。

公开(公告)号：US20130256774A1

公开(公告)日：2013-10-03

申请号：US13742940

申请日：2013-01-16

Applicant: Namho JEON ,  Jun-Su KIM ,  Satoru YAMADA ,  Jaehoon LEE ,  Seunguk HAN ,  Jiyoung KIM ,  Jin-Seong LEE

Inventor： Namho JEON ,  Jun-Su KIM ,  Satoru YAMADA ,  Jaehoon LEE ,  Seunguk HAN ,  Jiyoung KIM ,  Jin-Seong LEE

IPC: H01L29/78

CPC classification number: H01L29/7831 ,  G11C11/403 ,  G11C11/40615 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L27/105 ,  H01L27/115

Abstract: Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction.

Abstract translation: 半导体存储器件可以包括写入晶体管，其包括控制第一源极/漏极端子的第一写入栅极和控制沟道区域的第二写入栅极，以及读取晶体管，其包括连接到写入的第一源极/漏极端子的存储器节点栅极 晶体管。 第一写入门可以具有第一工作功能，并且第二写入门可以具有与第一工作功能不同的第二工作功能。 写晶体管的第一源极/漏极端子可以不具有PN结。

公开(公告)号：US20130093739A1

公开(公告)日：2013-04-18

申请号：US13419726

申请日：2012-03-14

Applicant: Ji-Sun KIM ,  Yeong-Keun KWON ,  Soo-Wan YOON ,  Young-Soo YOON ,  Jaehoon LEE ,  Chongchul CHAI

Inventor： Ji-Sun KIM ,  Yeong-Keun KWON ,  Soo-Wan YOON ,  Young-Soo YOON ,  Jaehoon LEE ,  Chongchul CHAI

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0434

Abstract: A display apparatus includes gate lines, data lines insulated from the gate lines while crossing the gate lines, and pixels each including sub-pixels in two successive rows by three successive columns. Among the sub-pixels in the two rows by the three columns, the sub-pixels in one of the three columns are respectively connected to a pair of different gate lines among three gate lines, and the sub-pixels in a different one of the three columns are connected to a remaining gate line among the three gate lines. The sub-pixels in the one and the different one of the three columns includes the same color filter and are applied with a gate signal transmitted in the same direction along pixel rows.

Abstract translation: 显示装置包括栅极线，与栅极线绝缘的数据线，同时跨越栅极线，以及每个包括具有三个连续列的两个连续行中的子像素的像素。 在三列中的两行中的子像素之中，三列之一中的一个子像素分别连接到三条栅极线中的一对不同的栅极线，并且不同的一个像素 三列连接到三条栅极线之间的剩余栅极线。 三列中的一个子像素和不同的一个子像素包括相同的滤色器，并施加沿像素行沿相同方向传输的栅极信号。

公开(公告)号：US20110316834A1

公开(公告)日：2011-12-29

申请号：US12982473

申请日：2010-12-30

Applicant: Chang Ho Lee ,  Jaehoon Lee

Inventor： Chang Ho Lee ,  Jaehoon Lee

IPC: G06F3/038 ,  H03K3/00

CPC classification number: G09G3/3677 ,  G09G2320/041 ,  G11C19/28

Abstract: A driving circuit includes a plurality of stages driven in response to a start signal. Each normal stage outputs a gate signal and a carry signal, increases an electric potential of a node in response to a previous carry signal of a previous stage, and decreases the gate signal to a first voltage in response to a carry signal from a next stage. Each stage applies a second voltage lower than the first voltage to the node in response to receipt of a carry signal from a second next stage. A first dummy stage outputs a first dummy carry signal to the last two normal stages in response to a last carry signal from the last normal stage and the start signal, and a second dummy stage outputs a second dummy carry signal to the last normal stage in response to the first dummy carry signal and the start signal.

Abstract translation: 驱动电路包括响应于起始信号而驱动的多个级。 每个正常级输出门信号和进位信号，响应于先前级的先前进位信号增加节点的电位，并且响应于来自下一级的进位信号而将栅极信号减小到第一电压 。 响应于接收到来自第二下一级的进位信号，每个阶段将比第一电压低的第二电压施加到节点。 第一伪级响应于来自最后正常级的最后进位信号和起始信号而将第一伪进位信号输出到最后两个正常级，并且第二虚拟级将第二伪进位信号输出到最后正常级 对第一伪进位信号和起始信号的响应。