公开(公告)号：US12125542B2

公开(公告)日：2024-10-22

申请号：US17695529

申请日：2022-03-15

Applicant: KIOXIA CORPORATION

Inventor： Wataru Moriyama ,  Hayato Konno ,  Takao Nakajima ,  Fumihiro Kono ,  Masaki Fujiu ,  Kiyoaki Iwasa ,  Tadashi Someya

IPC: G11C16/04 ,  G11C16/16 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

公开(公告)号：US12080374B2

公开(公告)日：2024-09-03

申请号：US17898888

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Masaki Fujiu ,  Hitoshi Shiga

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/065 ,  G11C7/12 ,  G11C7/222

Abstract: A semiconductor storage device includes a memory string, a sense amplifier connected to the memory string, first, second, third, and fourth latch circuits that are each connected to the sense amplifier, a first wiring connected to the sense amplifier, the first latch circuit and the second latch circuit, a second wiring connected to the third latch circuit, a third wiring connected to the fourth latch circuit, a first switch transistor between the first wiring and the third wiring, a second switch transistor between the first wiring and the second wiring, and a third switch transistor between the second wiring and the third wiring.