公开(公告)号：US12125542B2

公开(公告)日：2024-10-22

申请号：US17695529

申请日：2022-03-15

Applicant: KIOXIA CORPORATION

Inventor： Wataru Moriyama ,  Hayato Konno ,  Takao Nakajima ,  Fumihiro Kono ,  Masaki Fujiu ,  Kiyoaki Iwasa ,  Tadashi Someya

IPC: G11C16/04 ,  G11C16/16 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C16/0483 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

公开(公告)号：US11923020B2

公开(公告)日：2024-03-05

申请号：US17679667

申请日：2022-02-24

Applicant: Kioxia Corporation

Inventor： Hiroyuki Ishii ,  Yuji Nagai ,  Makoto Miakashi ,  Tomoko Kajiyama ,  Hayato Konno

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

公开(公告)号：US11195588B2

公开(公告)日：2021-12-07

申请号：US17012969

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hayato Konno ,  Akihiro Imamoto

IPC: G11C11/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/10

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell, and a first wiring and a second wiring electrically connected to the first memory cell and the second memory cell. In a write operation, a program operation starts at a first timing and a supply of a write pass voltage starts at a second timing. When a first command is received in a first period between the first timing and the second timing, the write operation is interrupted before the supply of the write pass voltage starts.