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公开(公告)号:US12080374B2
公开(公告)日:2024-09-03
申请号:US17898888
申请日:2022-08-30
Applicant: KIOXIA CORPORATION
Inventor: Masaki Fujiu , Hitoshi Shiga
Abstract: A semiconductor storage device includes a memory string, a sense amplifier connected to the memory string, first, second, third, and fourth latch circuits that are each connected to the sense amplifier, a first wiring connected to the sense amplifier, the first latch circuit and the second latch circuit, a second wiring connected to the third latch circuit, a third wiring connected to the fourth latch circuit, a first switch transistor between the first wiring and the third wiring, a second switch transistor between the first wiring and the second wiring, and a third switch transistor between the second wiring and the third wiring.
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公开(公告)号:US11158385B2
公开(公告)日:2021-10-26
申请号:US16841377
申请日:2020-04-06
Applicant: KIOXIA CORPORATION
Inventor: Koji Kato , Hitoshi Shiga
IPC: G11C16/26 , H01L27/1157 , G11C16/14 , G11C16/08 , G11C16/24 , G11C16/34 , G11C8/10 , G11C16/10 , G11C8/08 , G11C16/32 , H01L27/11582 , G11C16/04
Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.
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