公开(公告)号：US20200090753A1

公开(公告)日：2020-03-19

申请号：US16692233

申请日：2019-11-22

Applicant: KIOXIA CORPORATION

Inventor： Weihan WANG ,  Takahiro SHIMIZU ,  Noboru SHIBATA

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  H03M13/29 ,  G06F11/10 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

公开(公告)号：US20230072387A1

公开(公告)日：2023-03-09

申请号：US17682255

申请日：2022-02-28

Applicant: KIOXIA CORPORATION

Inventor： Takahiro SHIMIZU

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory string and a control circuit. The memory string includes a first memory cell connected to a first word line and a second memory cell adjacent to the first memory cell and connected to a second word line. The control circuit is configured to perform a multi-bit-data writing with respect to each of the first and second memory cells. The multi-bit-data writing includes, in order, a first programming to program the first memory cell, the first programming with respect to the second memory cell, a reading of first data from the first memory cell, a second programming to program the second memory cell, and a verification of data programmed in the second memory cell. The control circuit is configured to set a verify voltage to be applied to the second word line during the verification based on the first data.