公开(公告)号：US20240086096A1

公开(公告)日：2024-03-14

申请号：US18509572

申请日：2023-11-15

Applicant: KIOXIA CORPORATION

Inventor： Yuki SASAKI ,  Shinichi KANNO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0292

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.

公开(公告)号：US20240070006A1

公开(公告)日：2024-02-29

申请号：US18180234

申请日：2023-03-08

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Yuki SASAKI

IPC: G06F11/07 ,  G06F11/14

CPC classification number: G06F11/0772 ,  G06F11/076 ,  G06F11/1489

Abstract: According to one embodiment, when a code rate is less than 1, a controller encodes a plurality of pieces of write data to generate a codeword including the plurality of pieces of write data and one or more erasure recovery codes. The controller calculates a cumulative error count. The controller calculates at least one of a cumulative write amount or a cumulative read amount. The controller change the code rate such that the code rate is increased when a first value which is obtained by dividing the cumulative error count by the cumulative write amount or the cumulative read amount is less than a first threshold value, and the code rate is decreased when the first value is larger than or equal to a second threshold value.

公开(公告)号：US20230266915A1

公开(公告)日：2023-08-24

申请号：US18306068

申请日：2023-04-24

Applicant: KIOXIA CORPORATION

Inventor： Yuki SASAKI ,  Shinichi KANNO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F3/0611 ,  G06F12/0246 ,  G06F2212/7201

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.

公开(公告)号：US20230244383A1

公开(公告)日：2023-08-03

申请号：US17931300

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Yuki SASAKI

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/0653

Abstract: According to one embodiment, when a command being executed in a nonvolatile memory is an erase/program command and either a first condition or a second condition is satisfied, a memory system suspends an execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The first condition is that either the number of read commands included in the first command group or a sum of weights associated with the read commands is equal to or greater than a first value. The second condition is that one or more read commands are included in the first command group and a time elapsed from when an execution of the erase/program command is started or resumed becomes equal to or greater than a second value.

公开(公告)号：US20250094337A1

公开(公告)日：2025-03-20

申请号：US18788545

申请日：2024-07-30

Applicant: Kioxia Corporation

Inventor： Yuki SASAKI ,  Aurelien Nam Phong TRAN

IPC: G06F12/02

Abstract: According to one embodiment, a controller of a memory system provides a host with logical address spaces. A plurality of queues of the host include one or more queues allocated to each of the logical address spaces. The controller calculates first use amounts of a nonvolatile memory corresponding to the logical address spaces, respectively, selects a queue from which a command is to be fetched among the plurality of queues, based on the first use amounts, fetches a command from the queue, calculates a predicted use amount of the nonvolatile memory in accordance with the command, and updates a second use amount corresponding to a first logical address space to which the first queue is allocated among the first use amounts by using the predicted use amount.

公开(公告)号：US20220011964A1

公开(公告)日：2022-01-13

申请号：US17201004

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Yuki SASAKI ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.

公开(公告)号：US20240393970A1

公开(公告)日：2024-11-28

申请号：US18792186

申请日：2024-08-01

Applicant: Kioxia Corporation

Inventor： Yuki SASAKI ,  Shinichi KANNO

IPC: G06F3/06

Abstract: A memory system includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to set a block group of the nonvolatile memory to be in a writable state and generate in the volatile memory a list associated with the block group. The controller is configured to, with respect to a write command, add an entry to the list, which includes a first address of a host and a second address of the volatile memory, obtain the write data from the first address of the host and store the write data in the second address of the volatile memory, write the write data stored at the second address of the volatile memory into the block group, and upon the block group being fully written, set the block group to be in a non-writable state and dissociate the list from the block group.

公开(公告)号：US20230297247A1

公开(公告)日：2023-09-21

申请号：US17941388

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Yuki SASAKI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

Abstract: According to one embodiment, a controller of a memory system writes, in response to receiving from the host a write command specifying a logical address, data received from the host to a first write destination block. The controller manages a first list and first storage location information, the first list including a plurality of logical addresses corresponding respectively to write-uncompleted data, and the first storage location information indicating a storage location at a beginning of a write-uncompleted region in the first write destination block. In a case where a power loss has occurred without notice from the host, the controller writes the first list and the first storage location information to the nonvolatile memory using power from a capacitor.

公开(公告)号：US20250094345A1

公开(公告)日：2025-03-20

申请号：US18821905

申请日：2024-08-30

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Yuki SASAKI ,  Kensaku YAMAGUCHI

IPC: G06F12/02

Abstract: A memory system includes a non-volatile memory and a controller that is configured to: write N pieces of address translation information repeatedly in a first block according to a first order; write the N pieces of address translation information repeatedly in a second block of the non-volatile memory according to a second order that is offset from the first order by N/2; write an update log in the first and second blocks each time one of the N pieces is written; and in response to power to the memory system being restored after shutdown, read from the first block, N/2 pieces of address translation information and N/2 update logs last written thereinto, read from the second block, N/2 pieces of address translation information and N/2 update logs last written thereinto, and reconstruct a logical-to-physical address translation table from the information read from the non-volatile memory.

公开(公告)号：US20250094340A1

公开(公告)日：2025-03-20

申请号：US18967748

申请日：2024-12-04

Applicant: KIOXIA CORPORATION

Inventor： Yuki SASAKI ,  Shinichi KANNO ,  Takahiro KURITA

IPC: G06F12/02 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.