公开(公告)号：US20230161492A1

公开(公告)日：2023-05-25

申请号：US18089904

申请日：2022-12-28

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Tetsuya SUNATA ,  Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0679 ,  G06F3/0659 ,  G06F3/0604

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

公开(公告)号：US20210405900A1

公开(公告)日：2021-12-30

申请号：US17201559

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Tetsuya SUNATA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

公开(公告)号：US20230297514A1

公开(公告)日：2023-09-21

申请号：US17898307

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Takahiro KURITA ,  Shinichi KANNO

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory based on an address conversion table. The controller is configured to generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range, determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous, upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information, and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.

公开(公告)号：US20230401149A1

公开(公告)日：2023-12-14

申请号：US18457672

申请日：2023-08-29

Applicant: KIOXIA CORPORATION

Inventor： Yuki SASAKI ,  Shinichi KANNO ,  Takahiro KURITA

IPC: G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0246 ,  G06F12/1009 ,  G06F12/0207 ,  G06F2212/7209 ,  G06F2212/7201 ,  G06F2212/651

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.

公开(公告)号：US20220300172A1

公开(公告)日：2022-09-22

申请号：US17412028

申请日：2021-08-25

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Shinichi KANNO ,  Yuki SASAKI

IPC: G06F3/06

Abstract: A memory system may be connected to a host device. The memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory to reduce an amount of power consumption of the memory system based on a first instruction received from a host device connected to the memory system.

公开(公告)号：US20230333780A1

公开(公告)日：2023-10-19

申请号：US18337798

申请日：2023-06-20

Applicant: KIOXIA CORPORATION

Inventor： Takahiro KURITA ,  Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory is correspond to a first mode of writing data of N bits per unit area and a second mode of writing data of M bits (M>N) per unit area. When receiving a first command issued prior to a write command to instruct writing write data to the nonvolatile memory, the controller selects one or both of the first mode and the second mode for writing the write data to the nonvolatile memory, to allow writing the write data to the nonvolatile memory to be executed in the first mode as much as possible, based on a capacity of the write data specified by the first command and a capacity of a free area of the nonvolatile memory.

公开(公告)号：US20220300204A1

公开(公告)日：2022-09-22

申请号：US17410789

申请日：2021-08-24

Applicant: Kioxia Corporation

Inventor： Tetsuya SUNATA ,  Takumi FUJIMORI ,  Takahiro KURITA

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a write buffer. The memory controller receives commands stored in a queue by a host device from the queue. The memory controller receives a command stored in a queue by the host device from the queue and, in a state where first data not satisfying a write unit is stored in the write buffer, when receiving a first command for writing the first data to the nonvolatile memory from the queue, simultaneously writes the first data and second data acquired from the host device or a predetermined region of the volatile memory different from the write buffer to the nonvolatile memory.

公开(公告)号：US20220114090A1

公开(公告)日：2022-04-14

申请号：US17345438

申请日：2021-06-11

Applicant: Kioxia Corporation

Inventor： Yuki SASAKI ,  Shinichi KANNO ,  Takahiro KURITA

IPC: G06F12/02 ,  G06F12/1009

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.

公开(公告)号：US20230075796A1

公开(公告)日：2023-03-09

申请号：US17691938

申请日：2022-03-10

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.

公开(公告)号：US20220398201A1

公开(公告)日：2022-12-15

申请号：US17685962

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Masataka GOTO ,  Kohei OKUDA ,  Takahiro KURITA

IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/0891

Abstract: An information processing apparatus includes a network interface, a storage device, and a processor. The processor is configured to assign a plurality of zones in the storage device. Each of the zones is a contiguous physical address range of the storage device that is mapped to a contiguous logical address range. The processor is configured to generate zone management information for each of the plurality of zones, store content received from the origin server via the network interface, in one of writable zones and update a writable address of the zone management information for the one of the writable zones. The processor is configured to operate to transmit the received content, and control the storage device to delete data stored therein in units of a zone upon a predetermined cache clearing criteria being met.