公开(公告)号：US20250068354A1

公开(公告)日：2025-02-27

申请号：US18938627

申请日：2024-11-06

Applicant: Kioxia Corporation

Inventor： Hideki YOSHIDA ,  Shinichi KANNO ,  Naoki ESAKA

IPC: G06F3/06

Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

公开(公告)号：US20250013385A1

公开(公告)日：2025-01-09

申请号：US18892722

申请日：2024-09-23

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA

IPC: G06F3/06 ,  G06F12/0804

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

公开(公告)号：US20240393970A1

公开(公告)日：2024-11-28

申请号：US18792186

申请日：2024-08-01

Applicant: Kioxia Corporation

Inventor： Yuki SASAKI ,  Shinichi KANNO

IPC: G06F3/06

Abstract: A memory system includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to set a block group of the nonvolatile memory to be in a writable state and generate in the volatile memory a list associated with the block group. The controller is configured to, with respect to a write command, add an entry to the list, which includes a first address of a host and a second address of the volatile memory, obtain the write data from the first address of the host and store the write data in the second address of the volatile memory, write the write data stored at the second address of the volatile memory into the block group, and upon the block group being fully written, set the block group to be in a non-writable state and dissociate the list from the block group.

公开(公告)号：US20240319924A1

公开(公告)日：2024-09-26

申请号：US18735865

申请日：2024-06-06

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller is electrically coupled to the nonvolatile memory. The controller controls the nonvolatile memory. When receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.

公开(公告)号：US20240111416A1

公开(公告)日：2024-04-04

申请号：US18532267

申请日：2023-12-07

Applicant: Kioxia Corporation

Inventor： Kazuya KITSUNAI ,  Shinichi KANNO ,  Hirokuni YANO ,  Toshikatsu HIDA ,  Junji YANO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

公开(公告)号：US20240061574A1

公开(公告)日：2024-02-22

申请号：US18386631

申请日：2023-11-03

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06 ,  G11C29/52 ,  G06F12/02

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0679 ,  G11C29/52 ,  G06F12/0246 ,  G06F3/06 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

公开(公告)号：US20240036769A1

公开(公告)日：2024-02-01

申请号：US18484542

申请日：2023-10-11

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F3/064 ,  G06F3/0604

Abstract: According to one embodiment, a memory system determines a write destination block and a write destination location in the write destination block to which write data is to be written, and notifies a host of an identifier of the write data, a block address of the write destination block, and an offset indicative of the write destination location. The memory system retrieves the write data from a write buffer of the host, and writes the write data to the write destination location. In a case where a read command to designate a physical address of first data is received before a write operation of the first data is finished, the memory system reads the first data from the write buffer of the host.

公开(公告)号：US20230418739A1

公开(公告)日：2023-12-28

申请号：US18367547

申请日：2023-09-13

Applicant: Kioxia Corporation

Inventor： Shinichi KANNO ,  Hideki YOSHIDA

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F3/0679 ,  G06F3/0659 ,  G06F3/064 ,  G06F3/0688 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/067

Abstract: According to one embodiment, a memory system determine both of a first block to which data from a host is to be written and a first location of the first block, when receiving a write request to designate a first logical address from the host. The memory system writes the data from the host to the first location of the first block. The memory system notifies the host of the first logical address, a first block number designating the first block, and a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of grain having a size different from a page size.

公开(公告)号：US20230350607A1

公开(公告)日：2023-11-02

申请号：US18347905

申请日：2023-07-06

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0653 ,  G06F3/0604 ,  G06F3/0652

Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.

公开(公告)号：US20230297514A1

公开(公告)日：2023-09-21

申请号：US17898307

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Takahiro KURITA ,  Shinichi KANNO

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory based on an address conversion table. The controller is configured to generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range, determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous, upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information, and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.