INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD THAT ENSURES EFFECTIVE CACHING
    3.
    发明申请
    INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD THAT ENSURES EFFECTIVE CACHING 审中-公开
    信息处理器和信息处理方法可以实现有效的缓存

    公开(公告)号:US20150212946A1

    公开(公告)日:2015-07-30

    申请号:US14602879

    申请日:2015-01-22

    Inventor: Satoshi GOSHIMA

    CPC classification number: G06F12/0868 G06F12/0875 G06F2212/283 G06F2212/452

    Abstract: An information processor includes a CPU, a primary storage unit, a secondary storage unit, a cache memory, and a cache controller. The primary storage unit stores the at least one program and data. The data is used by at least one process generated by execution of the at least one program in the CPU. The secondary storage unit stores the at least one programs and the data. The secondary storage unit has a lower access speed than an access speed of the primary storage unit. The cache memory caches the data. The at least one process exchanges the data between the primary storage unit and the secondary storage unit. The cache controller controls the caching of the data based on caching necessity information, the caching necessity information being determined for each of the processes and indicating whether the caching of the data is necessary or not.

    Abstract translation: 信息处理器包括CPU,主存储单元,辅助存储单元,高速缓存存储器和高速缓存控制器。 主存储单元存储至少一个程序和数据。 该数据由至少一个通过执行CPU中的至少一个程序生成的处理使用。 辅助存储单元存储至少一个程序和数据。 次存储单元具有比主存储单元的访问速度更低的访问速度。 缓存存储器缓存数据。 所述至少一个进程在主存储单元和辅助存储单元之间交换数据。 高速缓存控制器基于缓存必要性信息来控制数据的缓存,为每个进程确定缓存必要性信息,并指示数据的高速缓存是否需要。

    STORAGE MEDIUM AND INFORMATION PROCESSING DEVICE FOR EXCHANGING DATA WITH SECONDARY STORAGE SECTION THROUGH CACHE
    4.
    发明申请
    STORAGE MEDIUM AND INFORMATION PROCESSING DEVICE FOR EXCHANGING DATA WITH SECONDARY STORAGE SECTION THROUGH CACHE 有权
    存储介质和信息处理设备,用于通过缓存进行二次存储部分交换数据

    公开(公告)号:US20160034402A1

    公开(公告)日:2016-02-04

    申请号:US14815437

    申请日:2015-07-31

    Inventor: Satoshi GOSHIMA

    CPC classification number: G06F12/0875 G06F9/3001 G06F2212/452

    Abstract: An information processing device includes a main control circuit including a central arithmetic processor that executes first processing through a first program, a sub-control circuit that executes second processing independently of the first processing, a primary storage circuit, and a secondary storage circuit. The secondary storage circuit has a slower access speed than the primary storage circuit. The secondary storage circuit stores a second program used for third processing executed once the first processing and the second processing are both complete. The main control circuit further includes a cache memory having a faster access speed than the secondary storage circuit and a cache controller. In a situation in which the second processing is not yet complete at a completion time of the first processing, the cache controller executes pre-reading of the second program from the secondary storage circuit and stores the second program into the cache memory.

    Abstract translation: 信息处理装置包括:主控制电路,包括通过第一程序执行第一处理的中央运算处理器,独立于第一处理执行第二处理的子控制电路,主存储电路和辅助存储电路。 辅助存储电路的访问速度比主存储电路慢。 一旦第一处理和第二处理完成,辅助存储电路存储用于第三处理的第二程序。 主控制电路还包括具有比辅助存储电路更快的访问速度的高速缓存存储器和高速缓存控制器。 在第一处理的完成时间的第二处理尚未完成的情况下,高速缓存控制器从二次存储电路执行第二程序的预读取,并将第二程序存储到高速缓冲存储器中。

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