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5 条记录 (耗时 0.018 秒)

    Cutting a ground plane to remove circuit board resonance
    2.
    发明授权
    Cutting a ground plane to remove circuit board resonance 失效
    切割地平面以消除电路板谐振

    公开(公告)号：US06665927B1

    公开(公告)日：2003-12-23

    申请号：US09474662

    申请日：1999-12-29

    申请人： Keith E. Dow ,  Russell N. Shryock

    发明人： Keith E. Dow ,  Russell N. Shryock

    IPC分类号： H01R4300

    CPC分类号： H05K1/0216 ,  H05K1/0225 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09663 ,  Y10T29/49117 ,  Y10T29/49155

    摘要： A method for decreasing resonance in a printed circuit board (PCB) uses cuts in a ground plane to slow a signal passing through the ground plane. Cuts in the ground plane may be used alone or in conjunction with the lengthening of signal traces. Slowing the signal passing through the ground plane enables a mismatch between the signal transit time of the ground plane and a signal oscillation period of the circuit board to be obtained. The mismatch results in decreased resonance.

    摘要翻译： 一种降低印刷电路板（PCB）谐振的方法使用接地平面中的切口来减慢通过接地平面的信号。 接地平面上的切割可以单独使用或与信号迹线延长一起使用。 降低通过接地层的信号能够使接地层的信号传播时间与要获得的电路板的信号振荡周期之间不匹配。 不匹配导致共振减少。

    Apparatus for improving signal transmission along parallel lines
    3.
    发明授权
    Apparatus for improving signal transmission along parallel lines 失效
    用于改善沿着平行线的信号传输的装置

    公开(公告)号：US5306967A

    公开(公告)日：1994-04-26

    申请号：US891233

    申请日：1992-05-29

    申请人： Keith E. Dow

    发明人： Keith E. Dow

    IPC分类号： H01L23/522 ,  H01L23/66 ,  H05K1/02 ,  H01L25/00

    CPC分类号： H01L23/522 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0216

    摘要： An apparatus for reducing signal degradation, propagation delay, and electromagnetic emission problems inherent in transmission of electrical signals along interconnect lines (such as lines which connect transistors in integrated circuits). The apparatus includes one or more pairs of generally parallel interconnect lines. Each line in each pair comprises line sections, and an inverter is connected between each pair of adjacent sections of each line. The inverters are arranged in staggered fashion, in the sense that the inverters connected along each line of a line pair are offset longitudinally from the inverters connected along the other line of the pair. Both bidirectional and unidirectional buses (groups of generally parallel interconnect line pairs) can be implemented in accordance with the invention. The invention can serve as the basis for increasing the speed of computers and other electrical devices, and permits tight packing of transistors and interconnect lines with minimal crosstalk between the lines.

    摘要翻译： 一种用于降低信号劣化，传播延迟以及沿着互连线（例如在集成电路中连接晶体管的线路）传输电信号所固有的电磁辐射问题的装置。 该装置包括一对或多对大致平行的互连线。 每对中的每一行包括线路部分，并且逆变器连接在每条线的每对相邻部分之间。 逆变器以交错的方式布置，这意味着沿着线对的每条线连接的逆变器从沿着该对的另一条线连接的逆变器纵向偏移。 双向和单向总线（大体上并联互连线对的组）可以根据本发明实现。 本发明可以作为增加计算机和其他电气设备的速度的基础，并且允许在线之间的串扰最小化的晶体管和互连线的紧密封装。

    Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings
    4.
    发明授权
    Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings 失效
    根据记录的相对相位设置的通过/失败指示确定的用于提高集成电路中的时序裕度的方法和装置

    公开(公告)号：US06910146B2

    公开(公告)日：2005-06-21

    申请号：US09992145

    申请日：2001-11-05

    申请人： Keith E. Dow

    发明人： Keith E. Dow

    IPC分类号： G06F1/10 ,  G06F1/04 ,  G01R31/26 ,  G01R31/28

    CPC分类号： G06F1/10

    摘要： Under the control of a processor executing a program, the timing margin of an electronic system can be improved by a series of operations that set the relative phase of receive and distributed clock signals from a number of given values, a relative phase of transmit and distributed clock signals from a number of given values, instruct an integrated circuit (IC) die to drive a sequence of outgoing data symbols and receive a sequence of incoming data symbols at those relative phase settings, and compares the outgoing symbols to the incoming symbols. A result of the comparison is recorded. The operations are repeated for other combinations of the discrete transmit and receive phase values. The relative phases are then set to a pair of values taken from the discrete transmit and receive phase values, which are closest to yielding a balanced timing margin as determined from the results of the comparisons.

    摘要翻译： 在执行程序的处理器的控制下，可以通过一系列操作来提高电子系统的定时裕度，所述一系列操作将接收和分布式时钟信号的相对相位设定为多个给定值，即传输和分布的相对相位 来自多个给定值的时钟信号，指示集成电路（IC）管芯驱动一系列输出数据符号并在这些相对相位设置下接收输入数据符号序列，并将输出符号与输入符号进行比较。 记录比较的结果。 对于离散发射和接收相位值的其他组合重复操作。 然后将相对相位设置为从离散的发射和接收相位值取得的一对值，其最接近于从比较结果确定的平衡时间裕度。

    Method for improving a timing margin in an integrated circuit by setting a relative phase of receive/transmit and distributed clock signals
    5.
    发明授权
    Method for improving a timing margin in an integrated circuit by setting a relative phase of receive/transmit and distributed clock signals 失效
    通过设置接收/发射和分布式时钟信号的相对相位来提高集成电路中的定时裕度的方法

    公开(公告)号：US06647507B1

    公开(公告)日：2003-11-11

    申请号：US09476976

    申请日：1999-12-31

    申请人： Keith E. Dow

    发明人： Keith E. Dow

    IPC分类号： G06F104

    CPC分类号： G06F1/10

    摘要： An embodiment of the invention includes an apparatus that has a first clock on a memory controller hub that is set to a first clock receive time and a second clock on the memory controller hub set to a first clock transmit time. A first data is sent from the memory to the memory controller hub. A second data is sent from the memory to the memory controller hub wherein the second data is checked. At least one of the first clock and the second clock has at least one of a second clock receive time and a second clock transmit time adjusted.

    摘要翻译： 本发明的实施例包括一种在存储器控制器集线器上具有设置为第一时钟接收时间的第一时钟和设置到第一时钟发送时间的存储器控​​制器集线器上的第二时钟的装置。 第一个数据从存储器发送到存储器控制器集线器。 第二数据从存储器发送到存储器控制器集线器，其中检查第二数据。 第一时钟和第二时钟中的至少一个具有调整的第二时钟接收时间和第二时钟发送时间中的至少一个。