公开(公告)号：US20230420054A1

公开(公告)日：2023-12-28

申请号：US18243258

申请日：2023-09-07

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20230052383A1

公开(公告)日：2023-02-16

申请号：US17973549

申请日：2022-10-26

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20210202007A1

公开(公告)日：2021-07-01

申请号：US17200996

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20250095748A1

公开(公告)日：2025-03-20

申请号：US18967232

申请日：2024-12-03

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.