公开(公告)号：US20230420054A1

公开(公告)日：2023-12-28

申请号：US18243258

申请日：2023-09-07

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20230082191A1

公开(公告)日：2023-03-16

申请号：US17993211

申请日：2022-11-23

Applicant: KIOXIA CORPORATION

Inventor： Akihiro IMAMOTO

IPC: G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08

Abstract: An operation method of a semiconductor storage device including a first memory die is provided. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks. The method includes starting a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks and starting a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks. At least part of the second write sequence is performed while the first write sequence is being performed.

公开(公告)号：US20230052383A1

公开(公告)日：2023-02-16

申请号：US17973549

申请日：2022-10-26

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20210202007A1

公开(公告)日：2021-07-01

申请号：US17200996

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US20250095748A1

公开(公告)日：2025-03-20

申请号：US18967232

申请日：2024-12-03

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Akihiro IMAMOTO ,  Toshifumi WATANABE ,  Mami KAKOI ,  Kohei MASUDA ,  Masahiro YOSHIHARA ,  Naofumi ABIKO

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.

公开(公告)号：US20220148656A1

公开(公告)日：2022-05-12

申请号：US17376638

申请日：2021-07-15

Applicant: KIOXIA CORPORATION

Inventor： Akihiro IMAMOTO

IPC: G11C16/10 ,  H01L25/065 ,  H01L25/18 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C16/08

Abstract: A semiconductor storage device includes a first memory die. The first memory die includes a first memory plane including a plurality of first memory blocks, a second memory plane including a plurality of second memory blocks, a first sequencer, and a second sequencer. The first sequencer is configured to start a first write sequence with respect to one of the first memory blocks in response to a first command set designating the one of the first memory blocks if no write sequence is being performed by the first sequencer. The second sequencer is configured to start a second write sequence with respect to one of the second memory blocks in response to a second command set designating the one of the second memory blocks if the first sequencer is performing the first write sequence and no write sequence is being performed by the second sequencer.

公开(公告)号：US20210193232A1

公开(公告)日：2021-06-24

申请号：US17012969

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hayato KONNO ,  Akihiro IMAMOTO

IPC: G11C16/26 ,  G11C16/30 ,  G11C16/10 ,  G11C16/34 ,  G11C16/32

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell, and a first wiring and a second wiring electrically connected to the first memory cell and the second memory cell. In a write operation, a program operation starts at a first timing and a supply of a write pass voltage starts at a second timing. When a first command is received in a first period between the first timing and the second timing, the write operation is interrupted before the supply of the write pass voltage starts.