-
公开(公告)号：US11532363B2
公开(公告)日：2022-12-20
申请号：US17200996
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
-
公开(公告)号：US11783899B2
公开(公告)日：2023-10-10
申请号：US17973549
申请日：2022-10-26
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
CPC classification number: G11C16/14 , G11C16/26 , G11C16/30 , G11C16/3445
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
-
公开(公告)号：US12198767B2
公开(公告)日：2025-01-14
申请号：US18243258
申请日：2023-09-07
Applicant: Kioxia Corporation
Inventor： Akio Sugahara , Akihiro Imamoto , Toshifumi Watanabe , Mami Kakoi , Kohei Masuda , Masahiro Yoshihara , Naofumi Abiko
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
-
-
Search Results
3
records
(took 0.01 seconds)
