公开(公告)号：US11532363B2

公开(公告)日：2022-12-20

申请号：US17200996

申请日：2021-03-15

申请人： Kioxia Corporation

发明人： Akio Sugahara ,  Akihiro Imamoto ,  Toshifumi Watanabe ,  Mami Kakoi ,  Kohei Masuda ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

摘要： A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

公开(公告)号：US11783899B2

公开(公告)日：2023-10-10

申请号：US17973549

申请日：2022-10-26

申请人： Kioxia Corporation

发明人： Akio Sugahara ,  Akihiro Imamoto ,  Toshifumi Watanabe ,  Mami Kakoi ,  Kohei Masuda ,  Masahiro Yoshihara ,  Naofumi Abiko

IPC分类号： G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445

摘要： A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.