公开(公告)号：US20210391001A1

公开(公告)日：2021-12-16

申请号：US17336451

申请日：2021-06-02

Applicant: Korea University Research and Business Foundation

Inventor： Jongsun PARK ,  Kyeongho LEE ,  Woong CHOI

IPC: G11C11/419 ,  G11C11/418

Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.

公开(公告)号：US20190244087A1

公开(公告)日：2019-08-08

申请号：US16253332

申请日：2019-01-22

Applicant: Korea University Research and Business Foundation

Inventor： Jongsun PARK ,  Woong CHOI ,  Kwanghyo JEONG

IPC: G06N3/063 ,  G06K9/62 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06K9/6267 ,  G06N3/04

Abstract: Disclosed are an artificial neural network device and a method of operating the same. The artificial neural network device includes an operation part performing an artificial neural network operation on an input feature map and a classification part performing a classifying operation on the input feature map based on the artificial neural network operation of the operation part. The operation part includes an XNOR operation circuit performing an XNOR operation on the input feature map and a filter and a binarizing circuit performing a binarization operation based on the result of the XNOR operation of the XNOR operation circuit. Accordingly, the artificial neural network device is miniaturized and performs the operation at high speed.

公开(公告)号：US20220028445A1

公开(公告)日：2022-01-27

申请号：US17377766

申请日：2021-07-16

Applicant: Korea University Research and Business Foundation

Inventor： Jongsun PARK ,  Kyeongho LEE ,  Woong CHOI

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094 ,  G06F7/544 ,  G06F7/523 ,  H03K19/173 ,  H03K19/21

Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.