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公开(公告)号：US20230420014A1
公开(公告)日：2023-12-28
申请号：US17987072
申请日：2022-11-15
Inventor： Jongsun PARK , Hyunchul PARK , Kyeongho LEE
IPC: G11C7/14 , G11C7/12 , G11C8/08 , H03K19/017
CPC classification number: G11C7/14 , G11C7/12 , G11C8/08 , H03K19/01721
Abstract: Embodiments of the present disclosure described herein relate to a computing in memory electronic device that supports current based analog operations and time based analog-to-digital conversion.
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2.发明申请公开(公告)号：US20210391001A1
公开(公告)日：2021-12-16
申请号：US17336451
申请日：2021-06-02
Inventor： Jongsun PARK , Kyeongho LEE , Woong CHOI
IPC: G11C11/419 , G11C11/418
Abstract: A computing in-memory device includes a memory cell array supporting a bitwise operation through at least one pair of memory cells activated in response to at least one pair of word line signals and a peripheral circuit connected to the at least one pair of memory cells via one pair of bit lines and performing a discharging operation on at least one bit line of the one pair of bit lines based on a voltage level of the one pair of bit lines.
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公开(公告)号：US20220028445A1
公开(公告)日：2022-01-27
申请号：US17377766
申请日：2021-07-16
Inventor： Jongsun PARK , Kyeongho LEE , Woong CHOI
IPC: G11C11/4091 , G11C11/4096 , G11C11/4094 , G06F7/544 , G06F7/523 , H03K19/173 , H03K19/21
Abstract: An in-memory computing device includes a memory cell array and a column peripheral circuit including a plurality of column peripheral units connected to a plurality of pairs of bit lines connected to the memory cell array. Each of the column peripheral units includes a sense amplifying and writing unit sensing and amplifying bitwise data through one pair of bit lines among the pairs of bit lines and an arithmetic logic unit performing an arithmetic operation with a full adder Boolean equation based on the bitwise data and performing a write back operation on operation data obtained by the arithmetic operation via the sense amplifying and writing unit.
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