Abstract:
A display device capable of driving at low speed is disclosed. Pixels connected to a first data line on odd-numbered display lines of a display panel are positioned on one side of the left and right sides of the first data line, and pixels connected to the first data line on even-numbered display lines of the display panel are positioned on the other side of the first data line based on a Z-inversion scheme. When a mode conversion control signal for switching to an interlaced low speed driving mode is input during a normal drive, in which a length of one frame is set to P, a timing controller expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2 and assigns a length P to each of n sub-frames of the one frame.
Abstract:
A display device includes an image signal processor generating modulation data of each pixel region corresponding to a display period of each frame based on an image signal and predetermined modulation value tables which are preset to different gains. The image signal processor includes a block divider and at least two data modulators. The block divider divides the display region into at least two block regions along a second direction. The at least two data modulators correspond to the at least two block regions, modulate gray scale data of each of pixel regions included in each block region based on a modulation value table, and generate modulation data of the pixel regions included in each block region. As a result, a difference in the charge amount caused by line resistance can be compensated according to the overdriving scheme, resulting in prevention of image quality deterioration.
Abstract:
A disclosed display device includes a display panel with a plurality of pixels and a plurality of signal lines respectively connected to the pixels, and a panel driving circuit to drive the signal lines. The display device further includes a timing controller to receive a first panel self-refresh (PSR) signal and an input image data from a host system, to sense whether the input image data has a preset video format based on the first PSR signal and, if the input image data is sensed to have the preset video format, to control the panel driving circuit to perform normal driving of the signal lines at a first frame frequency in a first group of frames and interlaced low-speed driving of the signal lines at a second frame frequency lower than the first frame frequency in a second group of frames to display the input image data.
Abstract:
A display device and method of driving the same are disclosed. The display device that transmits signals between a system board section and a circuit board section through an interface and uses Panel Self-Refresh (hereinafter, abbreviated as ‘PSR’) to reduce power consumption, the circuit board section comprising a PSR controller that, when a PSR On signal is supplied from the system board section, changes the operating frequency of a gate driver and data driver to a frequency higher than a reference frequency for driving the panel with PSR On, set by the system board section.
Abstract:
A display device capable of driving at low speed is disclosed. Pixels connected to a first data line on odd-numbered display lines of a display panel are positioned on one side of the left and right sides of the first data line, and pixels connected to the first data line on even-numbered display lines of the display panel are positioned on the other side of the first data line based on a Z-inversion scheme. When a mode conversion control signal for switching to an interlaced low speed driving mode is input during a normal drive, in which a length of one frame is set to P, a timing controller expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2 and assigns a length P to each of n sub-frames of the one frame.
Abstract:
A display device capable of driving at low speed includes a display panel, on which display lines each including a plurality of pixels are formed, a driver unit for driving the pixels, and a timing controller which controls an operation of the driver unit and includes a first control logic unit and a second control logic unit. When a mode conversion control signal of an on-level is input during a normal drive, in which a length of one frame is set to P, the first control logic unit expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2, assigns a length P to each of n sub-frames included in the one frame for the low speed drive, and controls the operation of the driver unit in an interlaced low speed driving scheme.
Abstract:
A display device capable of driving at low speed includes a display panel, on which display lines each including a plurality of pixels are formed, a driver unit for driving the pixels, and a timing controller which controls an operation of the driver unit and includes a first control logic unit and a second control logic unit. When a mode conversion control signal of an on-level is input during a normal drive, in which a length of one frame is set to P, the first control logic unit expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2, assigns a length P to each of n sub-frames included in the one frame for the low speed drive, and controls the operation of the driver unit in an interlaced low speed driving scheme.
Abstract:
A display device includes a display panel including data lines, a source driver positioned at one side of the display panel, and a timing controller which sequentially stores digital video data in a plurality of line memories, starts to generate an output data enable signal in conformity with a first writing start timing of a last line memory of the line memories, adjusts a pulse width of the output data enable signal of each horizontal pixel line based on a previously determined charge time graph, reads out the digital video data from the line memories in synchronization with rising edges of the output data enable signal, and generates a source output enable signal having the same pulse width each time each line memory finishes reading out the data.