Abstract:
A display device capable of driving at low speed includes a display panel, on which display lines each including a plurality of pixels are formed, a driver unit for driving the pixels, and a timing controller which controls an operation of the driver unit and includes a first control logic unit and a second control logic unit. When a mode conversion control signal of an on-level is input during a normal drive, in which a length of one frame is set to P, the first control logic unit expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2, assigns a length P to each of n sub-frames included in the one frame for the low speed drive, and controls the operation of the driver unit in an interlaced low speed driving scheme.
Abstract:
A display device capable of driving at low speed includes a display panel, on which display lines each including a plurality of pixels are formed, a driver unit for driving the pixels, and a timing controller which controls an operation of the driver unit and includes a first control logic unit and a second control logic unit. When a mode conversion control signal of an on-level is input during a normal drive, in which a length of one frame is set to P, the first control logic unit expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2, assigns a length P to each of n sub-frames included in the one frame for the low speed drive, and controls the operation of the driver unit in an interlaced low speed driving scheme.
Abstract:
A display device includes a display panel including data lines, a source driver positioned at one side of the display panel, and a timing controller which sequentially stores digital video data in a plurality of line memories, starts to generate an output data enable signal in conformity with a first writing start timing of a last line memory of the line memories, adjusts a pulse width of the output data enable signal of each horizontal pixel line based on a previously determined charge time graph, reads out the digital video data from the line memories in synchronization with rising edges of the output data enable signal, and generates a source output enable signal having the same pulse width each time each line memory finishes reading out the data.
Abstract:
A display device with built-in touch sensors comprises: a display panel with built-in touch sensors; and a touch driver that converts a sensed voltage of the touch sensors into sensed data, wherein the touch driver comprises: an enable signal generator that compares the sensed voltage with a preset offset voltage and outputs an enable signal at a first level if the sensed voltage is higher than or equal to the offset voltage and outputs the enable signal at a second level if the sensed voltage is lower than the offset voltage; and an analog-to-digital converter that converts the sensed voltage into the sensed data when the enable signal is at the first level.
Abstract:
A display device capable of driving at low speed is disclosed. Pixels connected to a first data line on odd-numbered display lines of a display panel are positioned on one side of the left and right sides of the first data line, and pixels connected to the first data line on even-numbered display lines of the display panel are positioned on the other side of the first data line based on a Z-inversion scheme. When a mode conversion control signal for switching to an interlaced low speed driving mode is input during a normal drive, in which a length of one frame is set to P, a timing controller expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2 and assigns a length P to each of n sub-frames of the one frame.
Abstract:
A display device and method of driving the same are disclosed. The display device that transmits signals between a system board section and a circuit board section through an interface and uses Panel Self-Refresh (hereinafter, abbreviated as ‘PSR’) to reduce power consumption, the circuit board section comprising a PSR controller that, when a PSR On signal is supplied from the system board section, changes the operating frequency of a gate driver and data driver to a frequency higher than a reference frequency for driving the panel with PSR On, set by the system board section.
Abstract:
A display device capable of driving at low speed is disclosed. Pixels connected to a first data line on odd-numbered display lines of a display panel are positioned on one side of the left and right sides of the first data line, and pixels connected to the first data line on even-numbered display lines of the display panel are positioned on the other side of the first data line based on a Z-inversion scheme. When a mode conversion control signal for switching to an interlaced low speed driving mode is input during a normal drive, in which a length of one frame is set to P, a timing controller expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2 and assigns a length P to each of n sub-frames of the one frame.