公开(公告)号：US20150319018A1

公开(公告)日：2015-11-05

申请号：US14288838

申请日：2014-05-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Niall Fitzgerald

IPC: H04L25/03 ,  H04L27/01

CPC classification number: G11C29/022 ,  G11C29/028 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03312 ,  H04L25/14 ,  H04L27/01 ,  H04L2025/03592

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract translation: 所描述的实施例在采用数据锁存器的接收机电路中提供调整数据锁存器的调整偏移以解决可能与锁存器的微调相互作用的锁存功能特征（例如，滞后和亚稳态）的电路。 根据所描述的实施例，修整过程在偏移电压斜坡的预选方向上运行，以平均化最终修整偏移选择的滞后和亚稳态的影响。 用于调整修整偏移的电路的累积限幅器“0”和“1”分辨率的不同阈值允许修剪运行次数的显着减少，加速切片器的修整处理，允许每当限幅器空闲时相对快速地确定修整偏移 。

公开(公告)号：US09197460B1

公开(公告)日：2015-11-24

申请号：US14288838

申请日：2014-05-28

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Lane A. Smith ,  Niall Fitzgerald

IPC: H04L25/03 ,  H04L27/01

CPC classification number: G11C29/022 ,  G11C29/028 ,  H04L25/03057 ,  H04L25/03159 ,  H04L25/03312 ,  H04L25/14 ,  H04L27/01 ,  H04L2025/03592

Abstract: Described embodiments provide for, in a receiver circuit employing a data latch, circuitry to adjust trim offset of the data latch to account for latch functional features (e.g., hysteresis and metastability) that may interact with trim of the latch. In accordance with the described embodiments, a trim procedure runs in a pre-selected directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. Different thresholds for accumulated slicer “0” and “1” discrimination of the circuitry to adjust trim offset allows for significant reduction in the number of trim runs, accelerating the slicers' trim process allowing for relatively quick determination of trim offset whenever the slicers are idle.

Abstract translation: 所描述的实施例在采用数据锁存器的接收机电路中提供调整数据锁存器的调整偏移以解决可能与锁存器的微调相互作用的锁存功能特征（例如，滞后和亚稳态）的电路。 根据所描述的实施例，修整过程在偏移电压斜坡的预选方向上运行，以平均化最终修整偏移选择的滞后和亚稳态的影响。 用于调整修整偏移的电路的累积限幅器“0”和“1”分辨率的不同阈值允许修剪运行次数的显着减少，加速切片器的修整处理，允许每当限幅器空闲时相对快速地确定修整偏移 。