公开(公告)号：US09478314B2

公开(公告)日：2016-10-25

申请号：US14486963

申请日：2014-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hungwei Lu ,  Wei-An Lai ,  Shuo-Nan Hung ,  Chi Lo

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C16/00 ,  G11C29/04

CPC classification number: G11C29/42 ,  G11C16/00 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.

Abstract translation: 集成电路存储器包括包括多条数据线的存储器阵列。 缓冲结构耦合到多条数据线，包括多个存储元件以存储多条数据线的位级状态值。 存储器包括基于相应束中的位的位级状态值来指示缓冲器结构中的对应的存储元件束的束级状态值的逻辑。 多个束状态电路被布置在菊花链中并且耦合到缓冲器结构中的各个束，从而产生指示在第一状态下检测束的菊花链的输出。 控制电路执行周期以确定菊花链的输出，每个周期清除捆绑状态电路，指示第一状态，如果输出指示在周期中处于第一状态的捆绑检测。