公开(公告)号：US20200051615A1

公开(公告)日：2020-02-13

申请号：US16658147

申请日：2019-10-20

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu ,  Shang-Pin Chen

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4096 ,  G06F13/40 ,  G11C5/04

Abstract: The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.

公开(公告)号：US20180322914A1

公开(公告)日：2018-11-08

申请号：US15959303

申请日：2018-04-23

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu ,  Shang-Pin Chen

IPC: G11C11/4093 ,  G06F3/06 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/4096

Abstract: The present invention provides a memory module wherein the memory module includes a plurality of memory devices having at least a first memory device and a second memory device, and the first memory device comprises a first termination resistor, and the second memory device comprises a second termination resistor. In the operations of the memory module, when the first memory device is accessed by a memory controller and the second memory device is not accessed by the memory controller, the first termination resistor is controlled to not provide impedance matching for the first memory device, and the second termination resistor is controlled to provide impedance matching for the second memory device.

公开(公告)号：US11790977B2

公开(公告)日：2023-10-17

申请号：US17349934

申请日：2021-06-17

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu ,  Ming-Hsin Yu

IPC: G11C11/4074 ,  G11C11/406 ,  G11C11/4094

CPC classification number: G11C11/4074 ,  G11C11/406 ,  G11C11/4094

Abstract: The present invention provides a memory controller including a plurality of channels. A first channel of the plurality of channels includes a first transmitter, a first pull-up variable resistor and a first pull-down variable resistor, wherein the first transmitter is configured to generate a first data signal to a memory module, the first pull-up variable resistor is coupled between a supply voltage and an output terminal of the first transmitter, and the first pull-down variable resistor is coupled to the output terminal of the first transmitter. The control circuit is coupled to the plurality of channels, and is configured to control the first pull-up variable resistor and/or the first pull-down variable resistor according to a reference voltage used by the memory module.

公开(公告)号：US11295802B2

公开(公告)日：2022-04-05

申请号：US16900981

申请日：2020-06-14

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu

IPC: H03F1/26 ,  G11C11/4074 ,  G05F3/20 ,  H03F3/45

Abstract: The present invention provides a circuit including a reference voltage generator and a plurality of receivers, wherein the reference voltage generator is configured to generate a reference voltage, and each of the receivers is configured to receive the reference voltage and a corresponding input signal to generate a corresponding output signal. In addition, for at least a specific receiver of the plurality of receivers, the specific receiver comprises at least one amplifying stage, the amplifying stage comprises a first input terminal configured to receive the corresponding input signal, a second input terminal configured to receive the reference voltage, a first output terminal configured to generate a first signal, and a second output terminal configured to generate a second signal; and the specific receiver further comprises a first feedback circuit coupled between the first output terminal and the second input terminal.

公开(公告)号：US20220020419A1

公开(公告)日：2022-01-20

申请号：US17349934

申请日：2021-06-17

Applicant: MEDIATEK INC.

Inventor： Chung-Hwa Wu ,  Ming-Hsin Yu

IPC: G11C11/4074 ,  G11C11/406 ,  G11C11/4094

Abstract: The present invention provides a memory controller including a plurality of channels. A first channel of the plurality of channels includes a first transmitter, a first pull-up variable resistor and a first pull-down variable resistor, wherein the first transmitter is configured to generate a first data signal to a memory module, the first pull-up variable resistor is coupled between a supply voltage and an output terminal of the first transmitter, and the first pull-down variable resistor is coupled to the output terminal of the first transmitter. The control circuit is coupled to the plurality of channels, and is configured to control the first pull-up variable resistor and/or the first pull-down variable resistor according to a reference voltage used by the memory module.