公开(公告)号：US20240019491A1

公开(公告)日：2024-01-18

申请号：US18207122

申请日：2023-06-07

Applicant: MEDIATEK INC.

Inventor： Jia-Horng Shieh ,  Po-Chao Tsao ,  Ming-Cheng Lee ,  Tung-Hsing Lee ,  Chi-Ming Lee ,  Yi-Ju Ting

IPC: G01R31/3185

CPC classification number: G01R31/318511

Abstract: A die-level electrical parameter extraction method includes: obtaining electrical parameters of a plurality of transistor types; obtaining measurement results of a plurality of logic blocks; estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks; and regarding a specific die of a wafer, obtaining die-level measurement of the plurality of logic blocks, and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results.

公开(公告)号：US11978734B2

公开(公告)日：2024-05-07

申请号：US18053944

申请日：2022-11-09

Applicant: MEDIATEK INC.

Inventor： Po-Chao Tsao

IPC: H01L27/088 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

公开(公告)号：US20240133949A1

公开(公告)日：2024-04-25

申请号：US18376447

申请日：2023-10-03

Applicant: MEDIATEK INC.

Inventor： Yu-Lin Yang ,  Chin-Wei Lin ,  Po-Chao Tsao ,  Tung-Hsing Lee ,  Chia-Jung Ni ,  Chi-Ming Lee ,  Yi-Ju Ting

IPC: G01R31/28 ,  G06N20/00

CPC classification number: G01R31/2894 ,  G06N20/00

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

公开(公告)号：US11424204B2

公开(公告)日：2022-08-23

申请号：US16928089

申请日：2020-07-14

Applicant: MEDIATEK Inc.

Inventor： Po-Chao Tsao ,  Yu-Hua Huang

IPC: H01L23/00

Abstract: A semiconductor component is provided. The semiconductor component includes a substrate and a pad. The pad has an upper surface and a slot, wherein the slot is recessed with respect to the upper surface.

公开(公告)号：US12165927B2

公开(公告)日：2024-12-10

申请号：US17369633

申请日：2021-07-07

Applicant: MediaTek Inc.

Inventor： Po-Chao Tsao

IPC: H01L21/8234 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

公开(公告)号：US11532617B2

公开(公告)日：2022-12-20

申请号：US17134694

申请日：2020-12-28

Applicant: MEDIATEK INC.

Inventor： Po-Chao Tsao

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure includes the first semiconductor stack and the second semiconductor stack formed over the first region and the second region of a substrate, respectively. The first and second semiconductor stacks extend in the first direction and are spaced apart from each other in the second direction. Each of the first semiconductor stack and the second semiconductor stack includes channel layers and a gate structure. The channel layers are formed above the substrate and are spaced apart from each other in the third direction. The gate structure includes the gate dielectric layers formed around the respective channel layers, and the gate electrode layer formed on the gate dielectric layers to surround the channel layers. The number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack.

公开(公告)号：US20250148273A1

公开(公告)日：2025-05-08

申请号：US18926397

申请日：2024-10-25

Applicant: MEDIATEK INC.

Inventor： Khim Jun Koh ,  Chi-Ming Lee ,  Yi-Ju Ting ,  Chung-Kai Chang ,  Po-Chao Tsao ,  Chin-Wei Lin ,  Yu-Lin Yang ,  Tung-Hsing Lee ,  Chin-Tang Lai

IPC: G06N3/0499

Abstract: In an aspect of the disclosure, a method for detecting outlier integrated circuits on a wafer is provided. The method comprises: operating multiple test items for each IC on the wafer to generate measured values of the multiple test items for each IC; selecting a target IC and neighboring ICs on the wafer repeatedly. each time after selecting the target IC executes the following steps: selecting a measured value of the target IC as a target measured value and selecting measured values of the target IC and the neighboring ICs as feature values of the target IC and the neighboring ICs; executing a transformer deep learning model to generate a predicted value of the target measured value; and identifying outlier ICs according to the predicted values of all the target ICs and the corresponding target measured values of all the target ICs.

公开(公告)号：US20210335675A1

公开(公告)日：2021-10-28

申请号：US17369633

申请日：2021-07-07

Applicant: MediaTek Inc.

Inventor： Po-Chao Tsao

IPC: H01L21/8234 ,  H01L21/74 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

公开(公告)号：US11094594B2

公开(公告)日：2021-08-17

申请号：US16059196

申请日：2018-08-09

Applicant: MEDIATEK INC.

Inventor： Po-Chao Tsao

IPC: H01L21/8234 ,  H01L21/74 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.

公开(公告)号：US20250148271A1

公开(公告)日：2025-05-08

申请号：US18915358

申请日：2024-10-15

Applicant: MEDIATEK INC.

Inventor： Yu-Lin Yang ,  Po-Chao Tsao ,  Hsiang-An Chen ,  Chin-Wei Lin ,  Ming-Cheng Lee ,  Tung-Hsing Lee

IPC: G06N3/0475

Abstract: An adaptive minimum voltage aging margin prediction method includes acquiring characteristic data of a plurality of dies in a testing line, predicting a wear-out failure rate of each module of the plurality of dies according to the characteristic data by using a neural network, and predicting a minimum voltage aging margin of the each module according to the wear-out failure rate of the each module by using the neural network.