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公开(公告)号：US09680454B2
公开(公告)日：2017-06-13
申请号：US14720838
申请日：2015-05-25
Applicant: MEDIATEK INC.
Inventor： Tzu-Chan Chueh , Yu-Li Hsueh
CPC classification number: H03K5/00006 , H03B19/14
Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.
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公开(公告)号：US20170111009A1
公开(公告)日：2017-04-20
申请号：US15262003
申请日：2016-09-11
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Tzu-Chan Chueh , Ang-Sheng Lin
IPC: H03B5/12
Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
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Patent Agency Ranking
公开(公告)号：US20160118964A1
公开(公告)日：2016-04-28
申请号：US14720838
申请日：2015-05-25
Applicant: MEDIATEK INC.
Inventor： Tzu-Chan Chueh , Yu-Li Hsueh
IPC: H03K5/00
CPC classification number: H03K5/00006 , H03B19/14
Abstract: A frequency tripler includes a double-frequency in-phase signal generator, a double-frequency quadrature signal generator and a mixer. The double-frequency in-phase signal generator is arranged for receiving at least an in-phase signal and a quadrature signal to generate a double-frequency in-phase signal whose frequency is twice that of the in-phase signal or the quadrature signal; the double-frequency quadrature signal generator is arranged for receiving at least the in-phase signal and the quadrature signal to generate a double-frequency quadrature signal whose frequency is twice that of the in-phase signal or the quadrature signal; and the mixer is arranged for receiving the in-phase signal, the quadrature signal, the double-frequency in-phase signal and the double-frequency quadrature signal to generate an output signal whose frequency is triple that of the in-phase signal or the quadrature signal.
Abstract translation: 频率三倍频器包括双频同相信号发生器，双频正交信号发生器和混频器。 双频同相信号发生器被布置成用于接收至少一个同相信号和一个正交信号以产生频率是同相信号或正交信号的两倍的双频同相信号; 双频正交信号发生器被布置用于至少接收同相信号和正交信号以产生其频率是同相信号或正交信号的两倍的双频正交信号; 混频器被配置为接收同相信号，正交信号，双频同相信号和双频正交信号，以产生其频率是同相信号的三倍的输出信号或 正交信号。
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公开(公告)号：US20220149849A1
公开(公告)日：2022-05-12
申请号：US17488339
申请日：2021-09-29
Applicant: MEDIATEK INC.
Inventor： Ang-Sheng Lin , Chun-Wei Chang , Tzu-Chan Chueh
Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
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公开(公告)号：US10425038B2
公开(公告)日：2019-09-24
申请号：US15262003
申请日：2016-09-11
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Tzu-Chan Chueh , Ang-Sheng Lin
Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
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公开(公告)号：US11456750B2
公开(公告)日：2022-09-27
申请号：US17488339
申请日：2021-09-29
Applicant: MEDIATEK INC.
Inventor： Ang-Sheng Lin , Chun-Wei Chang , Tzu-Chan Chueh
Abstract: A method of a phase-locked loop circuit includes: using a phase detector to generate a charging current signal according to an input frequency signal and a feedback signal; limiting a voltage level corresponding to the charging current signal in a voltage range according to a prediction signal to generate a digital output; performing a low-pass filter operation according to the digital output; generating a digital controlled oscillator (DCO) frequency signal according to an output of the loop filter; generating the feedback signal according to the DCO frequency signal; generating a phase signal, which indicates accumulated phase shift information, according to information of the feedback circuit and fractional frequency information; and, generating the prediction signal according to the phase signal.
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公开(公告)号：US11223362B2
公开(公告)日：2022-01-11
申请号：US17242395
申请日：2021-04-28
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Chiu , Ang-Sheng Lin , Tzu-Chan Chueh
Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.
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