公开(公告)号：US20180234473A1

公开(公告)日：2018-08-16

申请号：US15473668

申请日：2017-03-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Idan Burstein ,  Shlomi Museri ,  Richard Hastie

IPC: H04L29/06

Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.

公开(公告)号：US20180367589A1

公开(公告)日：2018-12-20

申请号：US15622094

申请日：2017-06-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Michael Kagan

IPC: H04L29/06 ,  H04N21/61 ,  H04N21/23

Abstract: Apparatus for data communications includes a host interface and a network interface, which receives from a packet communication network data packets containing video data comprising interleaved words of luminance data and chrominance data. In one embodiment, packet processing circuitry separates the luminance data from the chrominance data and writes the luminance data, via the host interface, to a luminance buffer in the host memory while writing the chrominance data, via the host interface, to at least one chrominance buffer in the memory, separate from the luminance buffer. In another embodiment, in which the video data include data words of more than eight bits, the packet processing circuitry writes the video data to at least one buffer while justifying the video data in the memory so that the video data with respect to successive pixels in the sequence are byte-aligned in the buffer.

公开(公告)号：US10516710B2

公开(公告)日：2019-12-24

申请号：US15473668

申请日：2017-03-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Idan Burstein ,  Shlomi Museri ,  Richard Hastie

IPC: G06F15/16 ,  H04L29/06 ,  H04L12/861 ,  H04L12/707 ,  H04L12/801

Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.

公开(公告)号：US20190140979A1

公开(公告)日：2019-05-09

申请号：US16012826

申请日：2018-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan Levi ,  Liran Liss ,  Haggai Eran ,  Noam Bloch ,  Idan Burstein ,  Lior Narkis ,  Avraham Ganor

IPC: H04L12/933 ,  G06F9/455 ,  G06F13/40

Abstract: A network interface controller that is connected to a host and a packet communications network. The network interface controller includes electrical circuitry configured as a packet processing pipeline with a plurality of stages. It is determined in the network interface controller that at least a portion of the stages of the pipeline are acceleration-defined stages. Packets are processed in the pipeline by transmitting data to an accelerator from the acceleration-defined stages, performing respective acceleration tasks on the transmitted data in the accelerator, and returning processed data from the accelerator to receiving stages of the pipeline.

公开(公告)号：US20180367465A1

公开(公告)日：2018-12-20

申请号：US15790075

申请日：2017-10-23

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi

IPC: H04L12/891 ,  H04L29/06 ,  H04L12/801

CPC classification number: H04L47/41 ,  H04L47/193 ,  H04L65/602 ,  H04L65/80 ,  H04L69/22 ,  H04N21/00

Abstract: An apparatus includes an input interface and transmit-side circuitry. The input interface is configured to receive a sequence of packets that carries a stream of video frames. The transmit-side circuitry is configured to divide the sequence of packets into multiple interleaved sub-sequences, wherein each sub-sequence carries a respective sub-stream of the stream of video frames, and wherein at least one of the sub-streams is self-contained and viewable independently of any other sub-stream, and to transmit the multiple sub-sequences of packets to a communication network over respective, different packet flows.

公开(公告)号：US11921662B2

公开(公告)日：2024-03-05

申请号：US17636484

申请日：2019-08-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Elad Mentovich ,  Ran Ravid ,  Roee Shapiro ,  Avraham Ganor ,  Paraskevas Bakopoulos ,  Dimitrios Kalavrouziotis

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/42

Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.

公开(公告)号：US10367750B2

公开(公告)日：2019-07-30

申请号：US15790075

申请日：2017-10-23

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi

IPC: H04L29/06 ,  H04L12/891 ,  H04L12/801

Abstract: An apparatus includes an input interface and transmit-side circuitry. The input interface is configured to receive a sequence of packets that carries a stream of video frames. The transmit-side circuitry is configured to divide the sequence of packets into multiple interleaved sub-sequences, wherein each sub-sequence carries a respective sub-stream of the stream of video frames, and wherein at least one of the sub-streams is self-contained and viewable independently of any other sub-stream, and to transmit the multiple sub-sequences of packets to a communication network over respective, different packet flows.

公开(公告)号：US20180150741A1

公开(公告)日：2018-05-31

申请号：US15813181

申请日：2017-11-15

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Tal Anker ,  Ohad Markus

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N3/08 ,  G06T2207/20084

Abstract: Described embodiments include a system that includes one or more buffers and circuitry. The circuitry is configured to process a plurality of input values, by identifying each of the input values that is not zero-valued, and, for each value of the identified input values, computing respective products of coefficients of a kernel with the value and storing at least some of the respective products in the buffers. The circuitry is further configured to compute a plurality of output values, by retrieving respective sets of stored values from the buffers, at least some of the retrieved sets including one or more of the products, and summing the retrieved sets. The circuitry is further configured to output the computed output values. Other embodiments are also described.