公开(公告)号：US20240364633A1

公开(公告)日：2024-10-31

申请号：US18307830

申请日：2023-04-27

Applicant: Mellanox Technologies, Ltd.

Inventor： Michael Weiner ,  Amit Hermony ,  Avi Urman ,  Idan Burstein ,  Yuval Shpigelman

IPC: H04L47/122 ,  H04L43/0852 ,  H04L47/11

CPC classification number: H04L47/122 ,  H04L43/0852 ,  H04L47/11

Abstract: A network device includes one or more ports, processing circuitry, and a memory-network congestion controller. The one or more ports are to connect to a network. The processing circuitry is to run a plurality of processing tasks that access a shared memory, one or more of the processing tasks including communicating one or more packet flows over the network. The memory-network congestion controller is to identify a memory-access congestion, which occurs in accessing the shared memory by one or more of the processing tasks, and to alleviate the memory-access congestion by causing a reduction in a communication rate of at least one of the packet flows.

公开(公告)号：US20240143526A1

公开(公告)日：2024-05-02

申请号：US17976909

申请日：2022-10-31

Applicant: Mellanox Technologies, Ltd.

Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221

Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

公开(公告)号：US20240089194A1

公开(公告)日：2024-03-14

申请号：US17990686

申请日：2022-11-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ariel Almog ,  Eitan Zahavi ,  Idan Burstein ,  Zachy Haramaty ,  Aviv Barnea

IPC: H04L45/00 ,  H04L67/1097 ,  H04L69/22

CPC classification number: H04L45/22 ,  H04L45/66 ,  H04L67/1097 ,  H04L69/22

Abstract: A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.

公开(公告)号：US11909855B2

公开(公告)日：2024-02-20

申请号：US18075460

申请日：2022-12-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

Abstract: In one embodiment, data communication apparatus includes packet processing circuitry to receive data from a memory responsively to a data transfer request, and cryptographically process the received data in units of data blocks using a block cipher so as to add corresponding cryptographically processed data blocks to a sequence of data packets, the sequence including respective ones of the cryptographically processed data blocks having block boundaries that are not aligned with payload boundaries of respective one of the packets, such that respective ones of the cryptographically processed data blocks are divided into two respective segments, which are contained in successive respective ones of the packets in the sequence, and a network interface which includes one or more ports for connection to a packet data network and is configured to send the sequence of data packets to a remote device over the packet data network via the one or more ports.

公开(公告)号：US11762785B2

公开(公告)日：2023-09-19

申请号：US17306033

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Ilan Pardo ,  Yamin Friedman ,  Michael Cotsford ,  Mark Rosenbluth ,  Hillel Chapman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/0811 ,  G06F15/78 ,  G06F12/02

CPC classification number: G06F13/1668 ,  G06F12/0246 ,  G06F12/0811 ,  G06F13/382 ,  G06F13/4221 ,  G06F15/7807 ,  G06F2213/0026

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

公开(公告)号：US11683266B2

公开(公告)日：2023-06-20

申请号：US17963216

申请日：2022-10-11

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

IPC: H04L45/00 ,  H04L45/42 ,  G06F11/10 ,  H04L69/163 ,  H04L69/22

CPC classification number: H04L45/566 ,  G06F11/1004 ,  H04L45/38 ,  H04L45/42 ,  H04L69/163 ,  H04L69/22

Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

公开(公告)号：US20220078043A1

公开(公告)日：2022-03-10

申请号：US17013677

申请日：2020-09-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Daniel Marcovitch ,  Idan Burstein ,  Liran Liss ,  Hillel Chapman ,  Dror Goldenberg ,  Michael Kagan ,  Aviad Yehezkel ,  Peter Paneah

IPC: H04L12/46 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173

Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

公开(公告)号：US11258887B2

公开(公告)日：2022-02-22

申请号：US16908776

申请日：2020-06-23

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Mark B. Rosenbluth ,  Idan Burstein ,  Rui Xu ,  Oded Lempel ,  Tsofia Eshel

IPC: H04L29/06 ,  G06F12/0875 ,  G06F13/40 ,  H04L12/879 ,  H04L29/08 ,  H04L69/22 ,  H04L49/901 ,  H04L69/324 ,  H04L67/568

Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

公开(公告)号：US11088966B2

公开(公告)日：2021-08-10

申请号：US16672682

申请日：2019-11-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Adi Menachem ,  Alex Shpiner ,  Noam Bloch ,  Eitan Zahavi ,  Idan Burstein ,  Dror Bohrer ,  Roee Moyal

IPC: H04L1/00 ,  H04L12/931 ,  H04L12/861 ,  H04L12/851 ,  H04L12/935

Abstract: A network adapter includes a host interface and circuitry. The host interface is configured to connect locally between the network adapter and a host via a bus. The circuitry is configured to receive from one or more source nodes, over a communication network to which the network adapter is coupled, multiple packets destined to the host, and temporarily store the received packets in a queue of the network adapter, to send the stored packets from the queue to the host over the bus, to monitor a performance attribute of the bus, and in response to detecting, based at least on the monitored performance attribute, an imminent overfilling state of the queue, send a congestion notification to at least one of the source nodes from which the received packets originated.

公开(公告)号：US20190034381A1

公开(公告)日：2019-01-31

申请号：US15659876

申请日：2017-07-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Diego Crupnicoff

IPC: G06F15/167 ,  G06F15/173 ,  H04L29/06

CPC classification number: G06F15/167 ,  G06F15/17331 ,  H04L67/1097 ,  H04L67/42

Abstract: Communication apparatus includes a host interface, configured to be coupled to a host processor having a host memory, and a network interface, which is configured to receive over a network from a sending node data packets conveying operations for execution in a sequential order on a predefined queue pair (QP), including at least a first packet conveying a posted write operation and a second packet conveying a non-posted write operation. Packet processing circuitry is configured to execute the posted write operation in accordance with the sequential order so as to write first data to the host memory prior to the execution of any subsequent operations in the sequential order, and to execute the non-posted write operation so as to write second data to the host memory while allowing one or more of the subsequent operations in the sequential order to be executed prior to completion of writing the second data.