公开(公告)号：US20220278693A1

公开(公告)日：2022-09-01

申请号：US17188696

申请日：2021-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Igal Kushnir ,  Eshel Gordon ,  Roi Levi

IPC: H03M1/66 ,  H04B1/04

Abstract: A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

公开(公告)号：US12294383B1

公开(公告)日：2025-05-06

申请号：US17151348

申请日：2021-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eshel Gordon ,  Boris Sharav ,  Roi Levi ,  Ayal Eshkoli

IPC: H03M1/66 ,  H02H9/04 ,  H03M1/36 ,  H03M1/68 ,  H03M3/00

Abstract: A digital-to-charge converter, a digital-to-analog converter, and a method of operating a digital-to-charge converter are provided. An illustrative method of operating a digital-to-charge converter is provided that includes: receiving a digital input signal at the digital to charge converter, charging one or more capacitors during a pre-evaluation period, where the one or more capacitors are charged with a supply voltage based the digital input signal, disconnecting the one or more capacitors from the supply voltage during an evaluation period, and generating an analog output signal from the digital to charge converter based on an evaluation of charge of the one or more capacitors during the evaluation period.

公开(公告)号：US11469768B2

公开(公告)日：2022-10-11

申请号：US17188696

申请日：2021-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Igal Kushnir ,  Eshel Gordon ,  Roi Levi

IPC: H03M1/66 ,  H04B1/04

Abstract: A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.