公开(公告)号：US20240056059A1

公开(公告)日：2024-02-15

申请号：US17884878

申请日：2022-08-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Igal Kushnir ,  Naor Peretz ,  Roi Levi

IPC: H03K3/017 ,  H03K19/17784 ,  H03K19/0185 ,  H04L25/03

CPC classification number: H03K3/017 ,  H03K19/17784 ,  H03K19/018521 ,  H04L25/03878

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

公开(公告)号：US20220278693A1

公开(公告)日：2022-09-01

申请号：US17188696

申请日：2021-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Igal Kushnir ,  Eshel Gordon ,  Roi Levi

IPC: H03M1/66 ,  H04B1/04

Abstract: A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

公开(公告)号：US11894847B1

公开(公告)日：2024-02-06

申请号：US17884878

申请日：2022-08-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Igal Kushnir ,  Naor Peretz ,  Roi Levi

IPC: H03K3/017 ,  H04L25/03 ,  H03K19/0185 ,  H03K19/17784

CPC classification number: H03K3/017 ,  H03K19/018521 ,  H03K19/17784 ,  H04L25/03878

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

公开(公告)号：US11469768B2

公开(公告)日：2022-10-11

申请号：US17188696

申请日：2021-03-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Igal Kushnir ,  Eshel Gordon ,  Roi Levi

IPC: H03M1/66 ,  H04B1/04

Abstract: A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

公开(公告)号：US12294383B1

公开(公告)日：2025-05-06

申请号：US17151348

申请日：2021-01-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eshel Gordon ,  Boris Sharav ,  Roi Levi ,  Ayal Eshkoli

IPC: H03M1/66 ,  H02H9/04 ,  H03M1/36 ,  H03M1/68 ,  H03M3/00

Abstract: A digital-to-charge converter, a digital-to-analog converter, and a method of operating a digital-to-charge converter are provided. An illustrative method of operating a digital-to-charge converter is provided that includes: receiving a digital input signal at the digital to charge converter, charging one or more capacitors during a pre-evaluation period, where the one or more capacitors are charged with a supply voltage based the digital input signal, disconnecting the one or more capacitors from the supply voltage during an evaluation period, and generating an analog output signal from the digital to charge converter based on an evaluation of charge of the one or more capacitors during the evaluation period.

公开(公告)号：US20240128954A1

公开(公告)日：2024-04-18

申请号：US18398779

申请日：2023-12-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Igal Kushnir ,  Naor Peretz ,  Roi Levi

IPC: H03K3/017 ,  H03K19/0185 ,  H03K19/17784 ,  H04L25/03

CPC classification number: H03K3/017 ,  H03K19/018521 ,  H03K19/17784 ,  H04L25/03878

Abstract: Technologies for duty cycle distortion (DCD) estimation are described. A transmitter includes a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier. The first CMOS amplifier receives an input signal and outputs an intermediate signal to the first attenuator. The first attenuator receives the intermediate signal and outputs an output signal having a signal swing that is less than a signal swing of the input signal. A first duty cycle correction (DCC) loop is coupled to the first output driver. The first DCC loop estimates first DCD in the intermediate signal output by the first CMOS amplifier.