公开(公告)号：US09325641B2

公开(公告)日：2016-04-26

申请号：US14207680

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Noam Katz Abramovich ,  George Elias ,  Ido Bukspan ,  Benny Koren ,  Gil Bloch

IPC: H04L12/861 ,  H04L12/801 ,  H04L12/803

CPC classification number: H04L49/90 ,  H04L47/115 ,  H04L47/122 ,  H04L47/18 ,  H04L47/283 ,  H04L47/30 ,  H04L49/3036

Abstract: A switching apparatus includes multiple ports, each including a respective buffer, and a switch controller. The switch controller is configured to concatenate the buffers of at least an input port and an output port selected from among the multiple ports for buffering traffic of a long-haul link, which is connected to the input port and whose delay exceeds buffering capacity of the buffer of the input port alone, and to carry out end-to-end flow control for the long haul link between the output port and the input port.

Abstract translation: 开关装置包括多个端口，每个端口包括相应的缓冲器和开关控制器。 交换机控制器被配置为连接至少一个输入端口和从多个端口中选择的输出端口的缓冲器，用于缓冲连接到输入端口并且其延迟超过缓冲容量的长途链路的流量 单独输入端口的缓冲区，并为输出端口和输入端口之间的长途链路执行端到端流控制。

公开(公告)号：US20150263994A1

公开(公告)日：2015-09-17

申请号：US14207680

申请日：2014-03-13

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Noam Katz Abramovich ,  George Elias ,  Ido Bukspan ,  Benny Koren ,  Gil Bloch

IPC: H04L12/861 ,  H04L12/803 ,  H04L12/801

CPC classification number: H04L49/90 ,  H04L47/115 ,  H04L47/122 ,  H04L47/18 ,  H04L47/283 ,  H04L47/30 ,  H04L49/3036

Abstract: A switching apparatus includes multiple ports, each including a respective buffer, and a switch controller. The switch controller is configured to concatenate the buffers of at least an input port and an output port selected from among the multiple ports for buffering traffic of a long-haul link, which is connected to the input port and whose delay exceeds buffering capacity of the buffer of the input port alone, and to carry out end-to-end flow control for the long haul link between the output port and the input port.

Abstract translation: 开关装置包括多个端口，每个端口包括相应的缓冲器和开关控制器。 交换机控制器被配置为连接至少一个输入端口和从多个端口中选择的输出端口的缓冲器，用于缓冲连接到输入端口并且其延迟超过缓冲容量的长途链路的流量 单独输入端口的缓冲区，并为输出端口和输入端口之间的长途链路执行端到端流控制。

公开(公告)号：US10462075B2

公开(公告)日：2019-10-29

申请号：US15470940

申请日：2017-03-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

IPC: H04L12/879 ,  H04L12/861

Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

公开(公告)号：US09641465B1

公开(公告)日：2017-05-02

申请号：US13972968

申请日：2013-08-22

Applicant: Mellanox Technologies Ltd.

Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

IPC: H04L12/861

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9094

Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

公开(公告)号：US20170201468A1

公开(公告)日：2017-07-13

申请号：US15470940

申请日：2017-03-28

Applicant: Mellanox Technologies, Ltd.

Inventor： Freddy Gabbay ,  Ido Bukshpan ,  Alon Webman ,  Miriam Menes ,  George Elias ,  Noam Katz Abramovich

IPC: H04L12/879 ,  H04L12/861

CPC classification number: H04L49/901 ,  H04L49/90 ,  H04L49/9094

Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

公开(公告)号：US09584429B2

公开(公告)日：2017-02-28

申请号：US14335962

申请日：2014-07-21

Applicant: Mellanox Technologies Ltd.

Inventor： Zachy Haramaty ,  Roy Kriss ,  Noam Katz Abramovich ,  George Elias ,  Ran Ravid

IPC: H04L12/801 ,  H04L12/807 ,  H04L12/863 ,  H04L12/825 ,  H04L12/835

CPC classification number: H04L47/39 ,  H04L47/263 ,  H04L47/30

Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.

Abstract translation: 一种用于通信的方法包括：通过接收节点的接收缓冲器中的通信链路存储从发送节点接收的分组。 接收缓冲器包括具有第一块大小的一个或多个块。 导出与接收缓冲器中的多个可用块相对应的第一信用计数。 第一信用计数被转换为第二信用计数，以便根据与第一块大小不同的第二块大小表示接收缓冲器中的可用空间。 发送节点的传输速率通过通过通信链路向发送节点发布第二信用计数来控制。

公开(公告)号：US20160021016A1

公开(公告)日：2016-01-21

申请号：US14335962

申请日：2014-07-21

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Zachy Haramaty ,  Roy Kriss ,  Noam Katz Abramovich ,  George Elias ,  Ran Ravid

IPC: H04L12/807 ,  H04L12/863 ,  H04L12/801

CPC classification number: H04L47/39 ,  H04L47/263 ,  H04L47/30

Abstract: A method for communication includes storing packets received from a sending node over a communication link in a receive buffer of a receiving node. The receive buffer includes one or more blocks having a first block size. A first credit count, corresponding to a number of available blocks in the receive buffer, is derived. The first credit count is converted to a second credit count so as to represent an available space in the receive buffer in accordance with a second block size, which is different from the first block size. A transmission rate of the sending node is controlled by publishing the second credit count to the sending node over the communication link.

Abstract translation: 一种用于通信的方法包括：通过接收节点的接收缓冲器中的通信链路存储从发送节点接收的分组。 接收缓冲器包括具有第一块大小的一个或多个块。 导出与接收缓冲器中的多个可用块相对应的第一信用计数。 第一信用计数被转换为第二信用计数，以便根据与第一块大小不同的第二块大小表示接收缓冲器中的可用空间。 发送节点的传输速率通过通过通信链路向发送节点发布第二信用计数来控制。