Simplified packet routing
    2.
    发明授权
    Simplified packet routing 有权
    简化包路由

    公开(公告)号:US09548960B2

    公开(公告)日:2017-01-17

    申请号:US14046976

    申请日:2013-10-06

    CPC classification number: H04L61/103 H04L12/18 H04L45/16 H04L45/745

    Abstract: A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.

    Abstract translation: 一种用于通信的方法,包括使用唯一地分配给每个节点的相应第3层地址在网络中的节点之间路由单播数据分组。 根据相应的第3层地址的算法映射,将相应的第2层单播地址分配给节点。 单播数据包使用分配的二层地址在网络的子网内转发。

    SIMPLIFIED PACKET ROUTING
    3.
    发明申请
    SIMPLIFIED PACKET ROUTING 有权
    简化分组路由

    公开(公告)号:US20150098466A1

    公开(公告)日:2015-04-09

    申请号:US14046976

    申请日:2013-10-06

    CPC classification number: H04L61/103 H04L12/18 H04L45/16 H04L45/745

    Abstract: A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.

    Abstract translation: 一种用于通信的方法,包括使用唯一地分配给每个节点的相应第3层地址在网络中的节点之间路由单播数据分组。 根据相应的第3层地址的算法映射,将相应的第2层单播地址分配给节点。 单播数据包使用分配的二层地址在网络的子网内转发。

    Communication over multiple virtual lanes using a shared buffer
    4.
    发明授权
    Communication over multiple virtual lanes using a shared buffer 有权
    使用共享缓冲区在多个虚拟通道上进行通信

    公开(公告)号:US08989011B2

    公开(公告)日:2015-03-24

    申请号:US13802926

    申请日:2013-03-14

    CPC classification number: H04L45/742 H04L47/125 H04L47/30 H04L47/39

    Abstract: A method for communication includes, in a sender node that sends packets to a receiver node over a physical link, making a decision, for a packet that is associated with a respective virtual link selected from among multiple virtual links, whether the receiver node is to buffer the packet in a dedicated buffer assigned to the respective virtual link or in a shared buffer that is shared among the multiple virtual links. The packet is sent, and the decision is signaled, from the sender node to the receiver node.

    Abstract translation: 一种用于通信的方法包括:在通过物理链路向接收方节点发送分组的发送方节点对与从多个虚拟链路中选择的相应虚拟链路相关联的分组作出决定,接收方节点是否 在分配给相应虚拟链路的专用缓冲器中或在多个虚拟链路之间共享的共享缓冲器中缓冲分组。 从发送方节点向接收方节点发送分组,并发送决定信号。

    DIRECT UPDATING OF NETWORK DELAY IN SYNCHRONIZATION PACKETS
    5.
    发明申请
    DIRECT UPDATING OF NETWORK DELAY IN SYNCHRONIZATION PACKETS 有权
    网络延迟在同步分组中的直接更新

    公开(公告)号:US20140241344A1

    公开(公告)日:2014-08-28

    申请号:US13778180

    申请日:2013-02-27

    CPC classification number: H04J3/0673 H04J3/0667 H04L43/0852

    Abstract: A method includes receiving in a network element a packet, which includes a delay field that indicates an overall time delay accumulated by the packet until arriving at the network element. Upon receiving the packet, an interim value is substituted in the delay field. The interim value is indicative of a difference between the overall time delay and an arrival time of the packet at the network element. Before sending the packet from the network element, the overall time delay is updated in the delay field based on the interim value and on a departure time at which the packet is to exit the network element. The packet, including the updated overall time delay, is transmitted from the network element.

    Abstract translation: 一种方法包括在网络元件中接收分组,分组包括指示由分组累积的总时间延迟直到到达网络元素的延迟字段。 在接收到分组后,在延迟字段中替换中间值。 中间值表示整个时间延迟与分组在网络元件的到达时间之间的差异。 在从网元发送分组之前,基于中间值和分组要离开网元的出发时间,在延迟字段中更新总时间延迟。 包括更新的总体时间延迟的分组从网络元件发送。

    Ethernet pause aggregation for a relay device

    公开(公告)号:US11888753B2

    公开(公告)日:2024-01-30

    申请号:US17398677

    申请日:2021-08-10

    CPC classification number: H04L47/32 H04L47/30

    Abstract: A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.

    Out-Of-Order Input / Output Write
    8.
    发明公开

    公开(公告)号:US20230376314A1

    公开(公告)日:2023-11-23

    申请号:US17748066

    申请日:2022-05-19

    CPC classification number: G06F9/3836 G06F9/30145 G06F9/30101 G06F9/30189

    Abstract: A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

    Queueing Systems
    10.
    发明申请
    Queueing Systems 审中-公开

    公开(公告)号:US20200371708A1

    公开(公告)日:2020-11-26

    申请号:US16416290

    申请日:2019-05-20

    Abstract: A network element including buffer address control circuitry for reading a given entry from a queue in a memory of a device external to the network element, the queue having at least a first entry and a last entry, the given entry including a destination address in the memory, output circuitry for writing data included in a packet received from external to the network element to the destination address in the memory in accordance with the given entry, and next entry assignment circuitry for assigning a next entry by: when the given entry is other than the last entry in the first queue, assigning the next entry to be an entry in the first queue after the given entry, and when the given entry is the last entry in the first queue, assigning the next entry to be the first entry in the first queue. Related apparatus and methods are also described.

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