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公开(公告)号：US11921662B2
公开(公告)日：2024-03-05
申请号：US17636484
申请日：2019-08-21
Applicant: Mellanox Technologies, Ltd.
Inventor： Dotan Levi , Elad Mentovich , Ran Ravid , Roee Shapiro , Avraham Ganor , Paraskevas Bakopoulos , Dimitrios Kalavrouziotis
CPC classification number: G06F13/4004 , G06F13/42
Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide a dynamic data interconnect and networking cable configuration. The dynamic data interconnect includes a substrate, transmitters supported on the substrate configured to generate signals, and receivers supported on the substrate configured to receive signals. The dynamic data interconnect further includes a number of connection pads that receive data cables attached thereto and a number of transmission lanes that operably couple the transmitters and receivers to the connection pads. The dynamic data interconnect further includes transmission circuitry in communication with each of the transmitters and receivers such that, in an operational configuration, the transmission circuitry determines a transmission state of the dynamic data interconnect and selectively disables operation of at least a portion of the transmitters or at least a portion of the receivers.
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公开(公告)号：US11637557B2
公开(公告)日：2023-04-25
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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公开(公告)号：US20240333423A1
公开(公告)日：2024-10-03
申请号：US18192239
申请日：2023-03-29
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Asaf Horev , Ran Ravid , Guy Lederman , Roman Meltser
IPC: H04L1/00
CPC classification number: H04L1/0057 , H04L1/0041
Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.
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公开(公告)号：US20240039689A1
公开(公告)日：2024-02-01
申请号：US17994326
申请日：2022-11-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Roman Meltser , Guy Lederman , Ran Ravid , Zvi Rechtman , Lavi Koch
IPC: H04L7/02
CPC classification number: H04L7/02
Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.
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公开(公告)号：US11283454B2
公开(公告)日：2022-03-22
申请号：US16920772
申请日：2020-07-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.
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Patent Agency Ranking
公开(公告)号：US08989011B2
公开(公告)日：2015-03-24
申请号：US13802926
申请日：2013-03-14
Applicant: Mellanox Technologies Ltd.
Inventor： Ran Ravid , Zachy Haramaty , Roy Kriss , Oded Wertheim
IPC: H04L12/801 , H04L12/747 , H04L12/879
CPC classification number: H04L45/742 , H04L47/125 , H04L47/30 , H04L47/39
Abstract: A method for communication includes, in a sender node that sends packets to a receiver node over a physical link, making a decision, for a packet that is associated with a respective virtual link selected from among multiple virtual links, whether the receiver node is to buffer the packet in a dedicated buffer assigned to the respective virtual link or in a shared buffer that is shared among the multiple virtual links. The packet is sent, and the decision is signaled, from the sender node to the receiver node.
Abstract translation: 一种用于通信的方法包括：在通过物理链路向接收方节点发送分组的发送方节点对与从多个虚拟链路中选择的相应虚拟链路相关联的分组作出决定，接收方节点是否 在分配给相应虚拟链路的专用缓冲器中或在多个虚拟链路之间共享的共享缓冲器中缓冲分组。 从发送方节点向接收方节点发送分组，并发送决定信号。
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公开(公告)号：US20240373378A1
公开(公告)日：2024-11-07
申请号：US18143509
申请日：2023-05-04
Applicant: Mellanox Technologies, Ltd.
Inventor： Natan Manevich , Dotan David Levi , Wojciech Wasko , Ran Ravid , Guy Lederman , Liron Mula , Eitan Zahavi , Peter Paneah
IPC: H04W56/00
Abstract: A system including a device coupled with a link and including a transmitter. The device is to generate a control block for synchronization via a physical layer of the link, the control block including a header portion of bits corresponding to a header indicating the message is a control block and a data portion of bits including synchronization information for synchronizing via the physical layer. The device is further to transmit, via the link, the control block comprising the header portion of bits and the data portion of bits.
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公开(公告)号：US20240056380A1
公开(公告)日：2024-02-15
申请号：US18174701
申请日：2023-02-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Zvi Rechtman , Guy Lederman , Stanislav Gurtovoy , Ran Ravid , Lavi Koch , Oded Nadir
Abstract: In one embodiment, a multi-segment communication network system includes nodes connected via links, a first node including a first receiver and transmitter, and a second node including a second receiver and transmitter, wherein the first transmitter is to transmit a link training frame including a training pattern to the second receiver, which is to receive the link training frame, the second node is to find a tuning factor to which to tune the first transmitter responsively to the training pattern, and generate a request indicative of the found tuning factor, the second transmitter is to send the request in the link training frame via a plurality of the links to the first receiver, the first receiver is to receive the request, and the first node is to tune at least one parameter of the first transmitter based on the tuning factor indicated in the request.
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公开(公告)号：US11552871B2
公开(公告)日：2023-01-10
申请号：US16900931
申请日：2020-06-14
Applicant: Mellanox Technologies, Ltd.
Inventor： Ran Sela , Liron Mula , Ran Ravid , Guy Lederman , Dotan David Levi
IPC: H04L43/106 , H04J3/06 , H04L43/0852 , G06F15/173 , H04L7/00
Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.
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公开(公告)号：US20220173741A1
公开(公告)日：2022-06-02
申请号：US17670540
申请日：2022-02-14
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ran Ravid , Aviv Berg , Lavi Koch , Chen Gaist , Dotan David Levi
Abstract: In one embodiment, a device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a receiver configured to receive a data stream from a remote clock source and recover a remote clock from the data stream, and a controller configured to find a clock differential between the local clock and the remote clock identified as a master dock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential between the local clock and the remote clock identified as the master clock so that the local clock generated by the PLL is synchronized with the master clock.
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